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The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market

The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc.

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    Date Created
    • 2012
    Resource Type
  • Text
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    Note
    • Partial requirement for: Ph.D., Arizona State University, 2012
      Note type
      thesis
    • Includes bibliographical references (p. 125-132)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Satendra Kumar Maurya

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