Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction.
Download count: 0
- Partial requirement for: M.S., Arizona State University, 2012Note typethesis
- Includes bibliographical references (p. 52-53)Note typebibliography
- Field of study: Electrical engineering