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Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast

Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction.

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    Date Created
    • 2012
    Resource Type
  • Text
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    Note
    • Partial requirement for: M.S., Arizona State University, 2012
      Note type
      thesis
    • Includes bibliographical references (p. 52-53)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Jyothi Swaroop Arlagadda Narasimharaju

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