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Combining the rapid development of semiconductor technologies, miniaturization of integrated circuits (ICs), and scaling down the device size is trending towards faster, cheaper, and more reliable components for low-power integrated circuits. Most research and development relate to efficiency, structure, materials, and performance. However, the thermal problem is also created and becomes more critical with shrinking device dimensions and increased integration densities, such that it affects the device performance and leads to degradation and damage. At the nanometer scale, the self-heating effect (SHE) is one of the main factors to degrade devices. Therefore, tracking and quantifying the SHE is important for reliability and efficiency issues. In this dissertation, engineers design two identical and closely spaced 40nm gate length silicon-on-insulator (SOI) n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) that share a common source with the same active silicon region. One of the MOSFETs acts as a heater to heat-up the active region, while the other one is a thermometer to evaluate the SHE and local temperature changes. The thermometer provides a method to calibrate the numerical models of self-heating and track the heat flow. Moreover, it also involves a trap-rich SOI wafer technology, in which a trap-rich layer, with higher resistivity and lower thermal conductivity compared to conventional bulk silicon substrates. The trap-rich SOI substrates can reduce the cross-talk and minimize the power consumption to increase the system performance. In particular, it offers a solution to radio frequency integrated circuits (RFICs) which require fast switching and low leakage. In high power amplifier (PA) applications, Watt-level PAs operates at less than 50% efficiency because of temperature limitations. The author uses experimental measurements of the local temperature changes, combined with simulations to examine the heat flow and temperature distribution. The approach may be useful to build a self-test application, because it can quantify the temperature changes by putting one or multiple NMOSFET thermometers around a complementary metal-oxide-semiconductor (CMOS) power amplifier, while only adding minimum die area. It points to ways in which it can optimize the reliability of RFIC applications, which operate under high-temperature or high-power conditions to protect the device before it is overheated or damaged.
ContributorsZhang, Xiong (Author) / Thornton, Trevor TT (Thesis advisor) / Vasileska, Dragica DV (Committee member) / Goryll, Michael MG (Committee member) / Myhajlenko, Stefan SM (Committee member) / Arizona State University (Publisher)
Created2020