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Description
Nanolasers represents the research frontier in both the areas of photonics and nanotechnology for its interesting properties in low dimension physics, its appealing prospects in integrated photonics, and other on-chip applications. In this thesis, I present my research work on fabrication and characterization of a new type of nanolasers: metallic

Nanolasers represents the research frontier in both the areas of photonics and nanotechnology for its interesting properties in low dimension physics, its appealing prospects in integrated photonics, and other on-chip applications. In this thesis, I present my research work on fabrication and characterization of a new type of nanolasers: metallic cavity nanolasers. The last ten years witnessed a dramatic paradigm shift from pure dielectric cavity to metallic cavity in the research of nanolasers. By using low loss metals such as silver, which is highly reflective at near infrared, light can be confined in an ultra small cavity or waveguide with sub-wavelength dimensions, thus enabling sub-wavelength cavity lasers. Based on this idea, I fabricated two different kinds of metallic cavity nanolasers with rectangular and circular geometries with InGaAs as the gain material and silver as the metallic shell. The lasing wavelength is around 1.55 μm, intended for optical communication applications. Continuous wave (CW) lasing at cryogenic temperature under current injection was achieved on devices with a deep sub-wavelength physical cavity volume smaller than 0.2 λ3. Improving device fabrication process is one of the main challenges in the development of metallic cavity nanolasers due to its ultra-small size. With improved fabrication process and device design, CW lasing at room temperature was demonstrated as well on a sub-wavelength rectangular device with a physical cavity volume of 0.67 λ3. Experiments verified that a small circular nanolasers supporting TE¬01 mode can generate an azimuthal polarized laser beam, providing a compact such source under electrical injection. Sources with such polarizations could have many special applications. Study of digital modulation of circular nanolasers showed that laser noise is an important factor that will affect the data rate of the nanolaser when used as the light source in optical interconnects. For future development, improving device fabrication processes is required to improve device performance. In addition, techniques need to be developed to realize nanolaser/Si waveguide integration. In essence, resolving these two critical issues will finally pave the way for these nanolasers to be used in various practical applications.
ContributorsDing, Kang (Author) / Ning, Cun-Zheng (Thesis advisor) / Yu, Hongbin (Committee member) / Palais, Joseph (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Inductors are fundamental components that do not scale well. Their physical limitations to scalability along with their inherent losses make them the main obstacle in achieving monolithic system-on-chip platform (SoCP). For past decades researchers focused on integrating magnetic materials into on-chip inductors in the quest of achieving high inductance density

Inductors are fundamental components that do not scale well. Their physical limitations to scalability along with their inherent losses make them the main obstacle in achieving monolithic system-on-chip platform (SoCP). For past decades researchers focused on integrating magnetic materials into on-chip inductors in the quest of achieving high inductance density and quality factor (QF). The state of the art on-chip inductor is made of an enclosed magnetic thin-film around the current carrying wire for maximum flux amplification. Though the integration of magnetic materials results in enhanced inductor characteristics, this approach has its own challenges and limitations especially in power applications. The current-induced magnetic field (HDC) drives the magnetic film into its saturation state. At saturation, inductance and QF drop to that of air-core inductors, eliminating the benefits of integrating magnetic materials. Increasing the current carrying capability without substantially sacrificing benefits brought on by the magnetic material is an open challenge in power applications. Researchers continue to address this challenge along with the continuous improvement in inductance and QF for RF and power applications.

In this work on-chip inductors incorporating magnetic Co-4%Zr-4%Ta -8%B thin films were fabricated and their characteristics were examined under the influence of an externally applied DC magnetic field. It is well established that spins in magnetic materials tend to align themselves in the same direction as the applied field. The resistance of the inductor resulting from the ferromagnetic film can be changed by manipulating the orientation of magnetization. A reduction in resistance should lead to decreases in losses and an enhancement in the QF. The effect of externally applied DC magnetic field along the easy and hard axes was thoroughly investigated. Depending on the strength and orientation of the externally applied field significant improvements in QF response were gained at the expense of a relative reduction in inductance. Characteristics of magnetic-based inductors degrade with current-induced stress. It was found that applying an externally low DC magnetic field across the on-chip inductor prevents the degradation in inductance and QF responses. Examining the effect of DC magnetic field on current carrying capability under low temperature is suggested.
ContributorsKhdour, Mahmoud (Author) / Yu, Hongbin (Thesis advisor) / Pan, George (Committee member) / Goryll, Michael (Committee member) / Bearat, Hamdallah (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Group III-nitride semiconductors have been commercially used in the fabrication of light-emitting diodes and laser diodes, covering the ultraviolet-visible-infrared spectral range and exhibit unique properties suitable for modern optoelectronic applications. InGaN ternary alloys have energy band gaps ranging from 0.7 to 3.4 eV. It has a great potential in

Group III-nitride semiconductors have been commercially used in the fabrication of light-emitting diodes and laser diodes, covering the ultraviolet-visible-infrared spectral range and exhibit unique properties suitable for modern optoelectronic applications. InGaN ternary alloys have energy band gaps ranging from 0.7 to 3.4 eV. It has a great potential in the application for high efficient solar cells. AlGaN ternary alloys have energy band gaps ranging from 3.4 to 6.2 eV. These alloys have a great potential in the application of deep ultra violet laser diodes. However, there are still many issues with these materials that remain to be solved. In this dissertation, several issues concerning structural, electronic, and optical properties of III-nitrides have been investigated using transmission electron microscopy. First, the microstructure of InxGa1-xN (x = 0.22, 0.46, 0.60, and 0.67) films grown by metal-modulated epitaxy on GaN buffer /sapphire substrates is studied. The effect of indium composition on the structure of InGaN films and strain relaxation is carefully analyzed. High luminescence intensity, low defect density, and uniform full misfit strain relaxation are observed for x = 0.67. Second, the properties of high-indium-content InGaN thin films using a new molecular beam epitaxy method have been studied for applications in solar cell technologies. This method uses a high quality AlN buffer with large lattice mismatch that results in a critical thickness below one lattice parameter. Finally, the effect of different substrates and number of gallium sources on the microstructure of AlGaN-based deep ultraviolet laser has been studied. It is found that defects in epitaxial layer are greatly reduced when the structure is deposited on a single crystal AlN substrate. Two gallium sources in the growth of multiple quantum wells active region are found to cause a significant improvement in the quality of quantum well structures.
ContributorsWei, Yong (Author) / Ponce, Fernando (Thesis advisor) / Chizmeshya, Andrew (Committee member) / McCartney, Martha (Committee member) / Menéndez, Jose (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2014
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Description
This dissertation aims to demonstrate a new approach to fabricating solar cells for spectrum-splitting photovoltaic systems with the potential to reduce their cost and complexity of manufacturing, called Monolithically Integrated Laterally Arrayed Multiple Band gap (MILAMB) solar cells. Single crystal semiconductor alloy nanowire (NW) ensembles are grown with the alloy

This dissertation aims to demonstrate a new approach to fabricating solar cells for spectrum-splitting photovoltaic systems with the potential to reduce their cost and complexity of manufacturing, called Monolithically Integrated Laterally Arrayed Multiple Band gap (MILAMB) solar cells. Single crystal semiconductor alloy nanowire (NW) ensembles are grown with the alloy composition and band gap changing continuously across a broad range over the surface of a single substrate in a single, inexpensive growth step by the Dual-Gradient Method. The nanowire ensembles then serve as the absorbing materials in a set of solar cells for spectrum-splitting photovoltaic systems.

Preliminary design and simulation studies based on Anderson's model band line-ups were undertaken for CdPbS and InGaN alloys. Systems of six subcells obtained efficiencies in the 32-38% range for CdPbS and 34-40% for InGaN at 1-240 suns, though both materials systems require significant development before these results could be achieved experimentally. For an experimental demonstration, CdSSe was selected due to its availability. Proof-of-concept CdSSe nanowire ensemble solar cells with two subcells were fabricated simultaneously on one substrate. I-V characterization under 1 sun AM1.5G conditions yielded open-circuit voltages (Voc) up to 307 and 173 mV and short-circuit current densities (Jsc) up to 0.091 and 0.974 mA/cm2 for the CdS- and CdSe-rich cells, respectively. Similar thin film cells were also fabricated for comparison. The nanowire cells showed substantially higher Voc than the film cells, which was attributed to higher material quality in the CdSSe absorber. I-V measurements were also conducted with optical filters to simulate a simple form of spectrum-splitting. The CdS-rich cells showed uniformly higher Voc and fill factor (FF) than the CdSe-rich cells, as expected due to their larger band gaps. This suggested higher power density was produced by the CdS-rich cells on the single-nanowire level, which is the principal benefit of spectrum-splitting. These results constitute a proof-of-concept experimental demonstration of the MILAMB approach to fabricating multiple cells for spectrum-splitting photovoltaics. Future systems based on this approach could help to reduce the cost and complexity of manufacturing spectrum-splitting photovoltaic systems and offer a low cost alternative to multi-junction tandems for achieving high efficiencies.
ContributorsCaselli, Derek (Author) / Ning, Cun-Zheng (Thesis advisor) / Tao, Meng (Committee member) / Yu, Hongbin (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014
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Description
In this work, a highly sensitive strain sensing technique is developed to realize in-plane strain mapping for microelectronic packages or emerging flexible or foldable devices, where mechanical or thermal strain is a major concern that could affect the performance of the working devices or even lead to the failure of

In this work, a highly sensitive strain sensing technique is developed to realize in-plane strain mapping for microelectronic packages or emerging flexible or foldable devices, where mechanical or thermal strain is a major concern that could affect the performance of the working devices or even lead to the failure of the devices. Therefore strain sensing techniques to create a contour of the strain distribution is desired.

The developed highly sensitive micro-strain sensing technique differs from the existing strain mapping techniques, such as digital image correlation (DIC)/micro-Moiré techniques, in terms of working mechanism, by filling a technology gap that requires high spatial resolution while simultaneously maintaining a large field-of-view. The strain sensing mechanism relies on the scanning of a tightly focused laser beam onto the grating that is on the sample surface to detect the change in the diffracted beam angle as a result of the strain. Gratings are fabricated on the target substrates to serve as strain sensors, which carries the strain information in the form of variations in the grating period. The geometric structure of the optical system inherently ensures the high sensitivity for the strain sensing, where the nanoscale change of the grating period is amplified by almost six orders into a diffraction peak shift on the order of several hundred micrometers. It significantly amplifies the small signal measurements so that the desired sensitivity and accuracy can be achieved.

The important features, such as strain sensitivity and spatial resolution, for the strain sensing technique are investigated to evaluate the technique. The strain sensitivity has been validated by measurements on homogenous materials with well known reference values of CTE (coefficient of thermal expansion). 10 micro-strain has been successfully resolved from the silicon CTE extraction measurements. Furthermore, the spatial resolution has been studied on predefined grating patterns, which are assembled to mimic the uneven strain distribution across the sample surface. A resolvable feature size of 10 µm has been achieved with an incident laser spot size of 50 µm in diameter.

In addition, the strain sensing technique has been applied to a composite sample made of SU8 and silicon, as well as the microelectronic packages for thermal strain mappings.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Poon, Poh Chieh Benny (Committee member) / Jiang, Hanqing (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density

Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books.
ContributorsYang, Xuan (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for

Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Semiconductor nanowires (NWs) are one dimensional materials and have size quantization effect when the diameter is sufficiently small. They can serve as optical wave guides along the length direction and contain optically active gain at the same time. Due to these unique properties, NWs are now very promising and extensively

Semiconductor nanowires (NWs) are one dimensional materials and have size quantization effect when the diameter is sufficiently small. They can serve as optical wave guides along the length direction and contain optically active gain at the same time. Due to these unique properties, NWs are now very promising and extensively studied for nanoscale optoelectronic applications. A systematic and comprehensive optical and microstructural study of several important infrared semiconductor NWs is presented in this thesis, which includes InAs, PbS, InGaAs, erbium chloride silicate and erbium silicate. Micro-photoluminescence (PL) and transmission electron microscope (TEM) were utilized in conjunction to characterize the optical and microstructure of these wires. The focus of this thesis is on optical study of semiconductor NWs in the mid-infrared wavelengths. First, differently structured InAs NWs grown using various methods were characterized and compared. Three main PL peaks which are below, near and above InAs bandgap, respectively, were observed. The octadecylthiol self-assembled monolayer was employed to passivate the surface of InAs NWs to eliminate or reduce the effects of the surface states. The band-edge emission from wurtzite-structured NWs was completely recovered after passivatoin. The passivated NWs showed very good stability in air and under heat. In the second part, mid-infrared optical study was conducted on PbS wires of subwavelength diameter and lasing was demonstrated under optical pumping. The PbS wires were grown on Si substrate using chemical vapor deposition and have a rock-salt cubic structure. Single-mode lasing at the wavelength of ~3000-4000 nm was obtained from single as-grown PbS wire up to the temperature of 115 K. PL characterization was also utilized to demonstrate the highest crystallinity of the vertical arrays of InP and InGaAs/InP composition-graded heterostructure NWs made by a top-down fabrication method. TEM-related measurements were performed to study the crystal structures and elemental compositions of the Er-compound core-shell NWs. The core-shell NWs consist of an orthorhombic-structured erbium chloride silicate shell and a cubic-structured silicon core. These NWs provide unique Si-compatible materials with emission at 1530 nm for optical communications and solid state lasers.
ContributorsSun, Minghua (Author) / Ning, Cun-Zheng (Thesis advisor) / Yu, Hongbin (Committee member) / Carpenter, Ray W. (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2011
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Description
A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to

A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
ContributorsSinha, Saurabh (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Yu, Hongbin (Committee member) / Christen, Jennifer B. (Committee member) / Arizona State University (Publisher)
Created2011
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Description
CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental

CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization.
ContributorsYe, Yun, Ph.D (Author) / Cao, Yu (Thesis advisor) / Yu, Hongbin (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence (Committee member) / Arizona State University (Publisher)
Created2011