Matching Items (25)
Description
In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.
ContributorsSoligo, Riccardo (Author) / Saraniti, Marco (Thesis advisor) / Goodnick, Stephen M (Committee member) / Chowdhury, Srabanti (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2016
Description
The Programmable Metallization Cell (PMC) is a novel solid-state resistive switching technology. It has a simple metal-insulator-metal “MIM” structure with one metal being electrochemically active (Cu) and the other one being inert (Pt or W), an insulating film (silica) acts as solid electrolyte for ion transport is sandwiched between these two electrodes. PMC’s resistance can be altered by an external electrical stimulus. The change of resistance is attributed to the formation or dissolution of Cu metal filament(s) within the silica layer which is associated with electrochemical redox reactions and ion transportation. In this dissertation, a comprehensive study of microfabrication method and its impacts on performance of PMC device is demonstrated, gamma-ray total ionizing dose (TID) impacts on device reliability is investigated, and the materials properties of doped/undoped silica switching layers are illuminated by impedance spectroscopy (IS). Due to the inherent CMOS compatibility, Cu-silica PMCs have great potential to be adopted in many emerging technologies, such as non-volatile storage cells and selector cells in ultra-dense 3D crosspoint memories, as well as electronic synapses in brain-inspired neuromorphic computing. Cu-silica PMC device performance for these applications is also assessed in this dissertation.
ContributorsChen, Wenhao (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh J (Thesis advisor) / Yu, Shimeng (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2017
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset.
ContributorsKim, Hyun-Tae (Author) / Bakkaloglu, Bertan (Thesis advisor) / Vermeire, Bert (Committee member) / Spanias, Andreas (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
Graphene, a one atomic thick planar sheet of carbon atoms, has a zero gap band structure with a linear dispersion relation. This unique property makes graphene a favorite for physicists and engineers, who are trying to understand the mechanism of charge transport in graphene and using it as channel material for field effect transistor (FET) beyond silicon. Therefore, an in-depth exploring of these electrical properties of graphene is urgent, which is the purpose of this dissertation. In this dissertation, the charge transport and quantum capacitance of graphene were studied. Firstly, the transport properties of back-gated graphene transistor covering by high dielectric medium were systematically studied. The gate efficiency increased by up to two orders of magnitude in the presence of a high top dielectric medium, but the mobility did not change significantly. The results strongly suggested that the previously reported top dielectric medium-induced charge transport properties of graphene FETs were possibly due to the increase of gate capacitance, rather than enhancement of carrier mobility. Secondly, a direct measurement of quantum capacitance of graphene was performed. The quantum capacitance displayed a non-zero minimum at the Dirac point and a linear increase on both sides of the minimum with relatively small slopes. The findings - which were not predicted by theory for ideal graphene - suggested that scattering from charged impurities also influences the quantum capacitance. The capacitances in aqueous solutions at different ionic concentrations were also measured, which strongly suggested that the longstanding puzzle about the interfacial capacitance in carbon-based electrodes had a quantum origin. Finally, the transport and quantum capacitance of epitaxial graphene were studied simultaneously, the quantum capacitance of epitaxial graphene was extracted, which was similar to that of exfoliated graphene near the Dirac Point, but exhibited a large sub-linear behavior at high carrier density. The self-consistent theory was found to provide a reasonable description of the transport data of the epitaxial graphene device, but a more complete theory was needed to explain both the transport and quantum capacitance data.
ContributorsXia, Jilin (Author) / Tao, N.J. (Thesis advisor) / Ferry, David (Committee member) / Thornton, Trevor (Committee member) / Tsui, Raymond (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2010
Description
Every engineer is responsible for completing a capstone project as a culmination of accredited university learning to demonstrate technical knowledge and enhance interpersonal skills, like teamwork, communication, time management, and problem solving. This project, with three or four engineers working together in a group, emphasizes not only the importance of technical skills acquired through laboratory procedures and coursework, but the significance of soft skills as one transitions from a university to a professional workplace; it also enhances the understanding of an engineer's obligation to ethically improve society by harnessing technical knowledge to bring about change. The CC2541 Smart SensorTag is a device manufactured by Texas Instruments that focuses on the use of wireless sensors to create low energy applications, or apps; it is equipped with Bluetooth Smart, which enables it to communicate wirelessly with similar devices like smart phones and computers, assisting greatly in app development. The device contains six built-in sensors, which can be utilized to track and log personal data in real-time; these sensors include a gyroscope, accelerometer, humidifier, thermometer, barometer, and magnetometer. By combining the data obtained through the sensors with the ability to communicate wirelessly, the SensorTag can be used to develop apps in multiple fields, including fitness, recreation, health, safety, and more. Team SensorTag chose to focus on health and safety issues to complete its capstone project, creating applications intended for use by senior citizens who live alone or in assisted care homes. Using the SensorTag's ability to track multiple local variables, the team worked to collect data that verified the accuracy and quality of the sensors through repeated experimental trials. Once the sensors were tested, the team developed applications accessible via smart phones or computers to trigger an alarm and send an alert via vibration, e-mail, or Tweet if the SensorTag detects a fall. The fall detection service utilizes the accelerometer and gyroscope sensors with the hope that such a system will prevent severe injuries among the elderly, allow them to function more independently, and improve their quality of life, which is the obligation of engineers to better through their work.
ContributorsMartin, Katherine Julia (Author) / Thornton, Trevor (Thesis director) / Goryll, Michael (Committee member) / Electrical Engineering Program (Contributor) / School of Film, Dance and Theatre (Contributor) / Barrett, The Honors College (Contributor)
Created2015-12
Description
This creative project is an extension of the work being done as part of Senior Design in<br/>developing the See-Through Car Pillar, a system designed to render the forward car pillars in a car<br/>invisible to the driver so they can have an unobstructed view utilizing displays, sensors, and a<br/>computer. The first half of the paper provides the motivation, design and progress of the project, <br/>while the latter half provides a literature survey on current automobile trends, the viability of the<br/>See-Through Car Pillar as a product in the market through case studies, and alternative designs and <br/>technologies that also might address the problem statement.
ContributorsRoy, Delwyn J (Author) / Thornton, Trevor (Thesis director) / Kozicki, Michael (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Wide Bandgap (WBG) semiconductor materials are shaping day-to-day technologyby introducing powerful and more energy responsible devices. These materials have
opened the door for building basic semiconductor devices which are superior in terms of
handling high voltages, high currents, power, and temperature which is not possible using
conventional silicon technology. As the research continues in the field of WBG based
devices, there is a potential chance that the power electronics industry can save billions of
dollars deploying energy-efficient circuits in high power conversion electronics. Diamond,
silicon carbide and gallium nitride are the top three contenders among which diamond can
significantly outmatch others in a variety of properties. However, diamond technology is
still in its early phase of development and there are challenges involved in many aspects of
processing a successful integrated circuit. The work done in this research addresses three
major aspects of problems related to diamond technology. In the first part, the applicability
of compact modeling and Technology Computer-Aided Design (TCAD) modeling
technique for diamond Schottky p-i-n diodes has been demonstrated. The compact model
accurately predicts AC, DC and nonlinear behavior of the diode required for fast circuit
simulation. Secondly, achieving low resistance ohmic contact onto n-type diamond is one
of the major issues that is still an open research problem as it determines the performance
of high-power RF circuits and switching losses in power converters circuits. So, another
portion of this thesis demonstrates the achievement of very low resistance ohmic contact
(~ 10-4 Ω⋅cm2) onto n-type diamond using nano crystalline carbon interface layer. Using
the developed TCAD and compact models for low resistance contacts, circuit level
predictions show improvements in RF performance. Lastly, an initial study of breakdown
characteristics of diamond and cubic boron nitride heterostructure is presented. This study
serves as a first step for making future transistors using diamond and cubic boron nitride –
a very less explored material system in literature yet promising for extreme circuit
applications involving high power and temperature.
ContributorsJHA, VISHAL (Author) / Thornton, Trevor (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Alford, Terry (Committee member) / Hoque, Mazhar (Committee member) / Arizona State University (Publisher)
Created2023
Description
Developing countries suffer from various health challenges due to inaccessible medical diagnostic laboratories and lack of resources to establish new laboratories. One way to address these issues is to develop diagnostic systems that are suitable for the low-resource setting. In addition to this, applications requiring rapid analyses further motivates the development of portable, easy-to-use, and accurate Point of Care (POC) diagnostics. Lateral Flow Immunoassays (LFIAs) are among the most successful POC tests as they satisfy most of the ASSURED criteria. However, factors like reagent stability, reaction rates limit the performance and robustness of LFIAs. The fluid flow rate in LFIA significantly affect the factors mentioned above, and hence, it is desirable to maintain an optimal fluid velocity in porous media.
The main objective of this study is to build a statistical model that enables us to determine the optimal design parameters and ambient conditions for achieving a desired fluid velocity in porous media. This study mainly focuses on the effects of relative humidity and temperature on evaporation in porous media and the impact of geometry on fluid velocity in LFIAs. A set of finite element analyses were performed, and the obtained simulation results were then experimentally verified using Whatman filter paper with different geometry under varying ambient conditions. Design of experiments was conducted to estimate the significant factors affecting the fluid flow rate.
Literature suggests that liquid evaporation is one of the major factors that inhibit fluid penetration and capillary flow in lateral flow Immunoassays. The obtained results closely align with the existing literature and conclude that a desired fluid flow rate can be achieved by tuning the geometry of the porous media. The derived statistical model suggests that a dry and warm atmosphere is expected to inhibit the fluid flow rate the most and vice-versa.
The main objective of this study is to build a statistical model that enables us to determine the optimal design parameters and ambient conditions for achieving a desired fluid velocity in porous media. This study mainly focuses on the effects of relative humidity and temperature on evaporation in porous media and the impact of geometry on fluid velocity in LFIAs. A set of finite element analyses were performed, and the obtained simulation results were then experimentally verified using Whatman filter paper with different geometry under varying ambient conditions. Design of experiments was conducted to estimate the significant factors affecting the fluid flow rate.
Literature suggests that liquid evaporation is one of the major factors that inhibit fluid penetration and capillary flow in lateral flow Immunoassays. The obtained results closely align with the existing literature and conclude that a desired fluid flow rate can be achieved by tuning the geometry of the porous media. The derived statistical model suggests that a dry and warm atmosphere is expected to inhibit the fluid flow rate the most and vice-versa.
ContributorsThamatam, Nipun (Author) / Christen, Jennifer Blain (Thesis advisor) / Goryll, Michael (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019