Matching Items (7)
Description
Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.
ContributorsKao, Wei-Chieh (Author) / Goryll, Michael (Thesis advisor) / Chowdhury, Srabanti (Committee member) / Yu, Hongbin (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2015
Description
Silicon carbide (SiC), long touted as a material that can satisfy the specific property requirements for high temperature and high power applications, was studied quantitatively using various techniques. The electronic band structure of 4H SiC is examined in the first half of this dissertation. A brief introduction to band structure calculations, with particular emphasis on the empirical pseudopotential method, is given as a foundation for the subsequent work. Next, the crystal pseudopotential for 4H SiC is derived in detail, and a novel approach using a genetic algorithm search routine is employed to find the fitting parameters needed to generate the band structure. Using this technique, the band structure is fitted to experimentally measured energy band gaps giving an indirect band gap energy of 3.28 eV, and direct f¡, M, K and L energy transitions of 6.30, 4.42, 7.90 and 6.03 eV, respectively. The generated result is also shown to give effective mass values of mMf¡*=0.66m0, mMK*=0.31m0, mML*=0.34m0, in close agreement with experimental results. The second half of this dissertation discusses computational work in finding the electron Hall mobility and Hall scattering factor for 6H SiC. This disscussion begins with an introductory chapter that gives background on how scattering rates are dervied and the specific expressions for important mechanisms. The next chapter discusses mobility calculations for 6H SiC in particular, beginnning with Rode's method to solve the Boltzmann transport equation. Using this method and the transition rates of the previous chapter, an acoustic deformation potential DA value of 5.5 eV, an inter-valley phonon deformation potential Dif value of 1.25~1011 eV/m and inter-valley phonon energy ℏfÖif of 65 meV that simultaneously fit experimental data on electron Hall mobility and Hall scattering factor was found.
ContributorsNg, Garrick (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Skromme, Brian (Committee member) / Alford, Terry (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2010
Description
Recently, the implementation of neuromorphic accelerator hardware has gradually changed from traditional Von Neumann architectures to non-Von Neumann architectures due to the “memory wall” and “power wall”. Near-memory computing (NMC) and In- memory computing (IMC) are two common types of non-Von Neumann approaches. NMC can help reduce data movements, yet it cannot fully address the challenge of improving computational efficiency as the neural network size grows. IMC has been proposed as a superior alternative. This architecture performs computation inside the memory array using stackable synaptic devices to improve the latency and the energy efficiency of neural network accelerators. Both volatile and non-volatile computational memory devices can achieve IMC. Fully complementary metal-oxide semiconductor (CMOS) in-memory computing cells can be realized by adding additional transistors in standard static random access memory (SRAM) bit-cell. The SRAM-based designs investigated in this dissertation perform bit-wise logical operation to obtain XNOR-and-accumulate computation (XAC) for deep neural networks (DNNs). Hybrid in-memory computing architectures combine CMOS with embedded non-volatile memory (eNVM). Resistive random access memory (RRAM) is one class of eNVM ideally suited for hybrid IMC. In a neural network, RRAM with programmable multi-level resistance/conductance states can naturally emulate weight transitions in the synaptic elements of neural networks. In this dissertation, the operation and effects of ionizing radiation effects on both fully CMOS and hybrid IMCs are investigated. The fully CMOS architectures preform SRAM-based XAC computations. The hybrid architectures use multi-state RRAM synapse with CMOS neurons to perform multiply-and-accumulate computation (MAC). In the SRAM XAC array, an 8×8 XNOR IMC array is modeled with flipped-well enhanced-gate super low threshold voltage (EGSLVT) metal-oxide semiconductor field-effect transistors (MOSFETs) from the GlobalFoundries 22nm fully depleted silicon on insulator (FDSOI) process. The impact of total ionizing dose (TID) on the XAC synaptic array is analyzed by using radiation-aware models to mimic TID-induced voltage shifts in MOSFETs. In multi- state RRAM MAC array, 4-state conductance has been programmed in hafnium-oxide (HfOx) RRAM 1-transistor-1-resistor (1T1R) array. The impact of total ionizing dose on the multi-state behavior of HfOx RRAM is evaluated by irradiating a 64kb 1T1R array with 90nm CMOS peripheral circuitry under Co-60 γ-ray irradiation.
ContributorsHan, Xu (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Marinella, Matthew (Committee member) / Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2022
Description
The Deep Neural Network (DNN) is one type of a neuromorphic computing approach that has gained substantial interest today. To achieve continuous improvement in accuracy, the depth, and the size of the deep neural network needs to significantly increase. As the scale of the neural network increases, it poses a severe challenge to its hardware implementation with conventional Computer Processing Unit (CPU) and Graphic Processing Unit (GPU) from the perspective of power, computation, and memory. To address this challenge, domain specific specialized digital neural network accelerators based on Field Programmable Gate Array (FPGAs) and Application Specific Integrated Circuits (ASICs) have been developed. However, limitations still exist in terms of on-chip memory capacity, and off-chip memory access. As an alternative, Resistive Random Access Memories (RRAMs), have been proposed to store weights on chip with higher density and enabling fast analog computation with low power consumption. Conductive Bridge Random Access Memories (CBRAMs) is a subset of RRAMs, whose conductance states is defined by the existence and modulation of a conductive metal filament. Ag-Chalcogenide based Conductive Bridge RAM (CBRAM) devices have demonstrated multiple resistive states making them potential candidates for use as analog synapses in neuromorphic hardware. In this work the use of Ag-Ge30Se70 device as an analog synaptic device has been explored. Ag-Ge30Se70 CBRAM crossbar array was fabricated. The fabricated crossbar devices were subjected to different pulsing schemes and conductance linearity response was analyzed. An improved linear response of the devices from a non-linearity factor of 6.65 to 1 for potentiation and -2.25 to -0.95 for depression with non-identical pulse application is observed. The effect of improved linearity was quantified by simulating the devices in an artificial neural network. Simulations for area, latency, and power consumption of the CBRAM device in a neural accelerator was conducted. Further, the changes caused by Total Ionizing Dose (TID) in the conductance of the analog response of Ag-Ge30Se70 Conductive Bridge Random Access Memory (CBRAM)-based synapses are studied. The effect of irradiation was further analyzed by simulating the devices in an artificial neural network. Material characterization was performed to understand the change in conductance observed due to TID.
ContributorsApsangi, Priyanka (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2022
Description
Machine learning advancements have led to increasingly complex algorithms, resulting in significant energy consumption due to heightened memory-transfer requirements and inefficient vector matrix multiplication (VMM). To address this issue, many have proposed ReRAM analog in-memory computing (AIMC) as a solution. AIMC enhances the time-energy efficiency of VMM operations beyond conventional VMM digital hardware, such as a tensor processing unit (TPU), while substantially reducing memory-transfer demands through in-memory computing. As AIMC gains prominence as a solution, it becomes crucial to optimize ReRAM and analog crossbar architecture characteristics. This thesis introduces an application-specific integrated circuit (ASIC) tailored forcharacterizing ReRAM within a crossbar array architecture and discusses the interfacing techniques employed. It discusses ReRAM forming and programming techniques and showcases chip’s ability to utilize the write-verify programming method to write image pixels on a conductance heat map. Additionally, this thesis assesses the ASIC’s capability to characterize different aspects of ReRAM, including drift and noise characteristics. The research employs the chip to extract ReRAM data and models it within a crossbar array simulator, enabling its application in the classification of the CIFAR-10 dataset.
ContributorsShort, Jesse (Author) / Marinella, Matthew (Thesis advisor) / Barnaby, Hugh (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Arizona State University (Publisher)
Created2023
Description
Modern Complementary-Metal-Oxide-Semiconductor (CMOS) technologies are facing critical challenges: scaling channel lengths below ~10 nm is hindered by significant transport degradation as bulk semiconductors (i.e., silicon) are thinned down, energy consumption is affected by short-channel effects and off-state leakage, and conventional von Neumann computing architectures face serious bottlenecks affecting performance and efficiency (energy consumption and throughput). Neuromorhic and/or in-memory computing architectures using resistive random-access memory (RRAM) crossbar arrays are promising candidates to mitigate these bottlenecks and to circumvent CMOS scaling challenges. Recently, emerging two dimensional materials (2DMs) are investigated towards ultra-scaled CMOS devices, as well as towards non-volatile memory and neuromorphic devices with potential improvements in scalability, power consumption, switching speed, and compatibility with CMOS integration.The first part of this dissertation presents contributions towards high-yield 2DMs field- effect-transistors (FETs) fabrication using wafer-scale chemical vapor deposition (CVD) monolayer MoS2. This work provides valuable insight about metal contact processing, including extraction of Schottky barrier heights and Fermi-level pinning effects, for next- generation integrated electronic systems based on CVD-grown 2DMs.
The second part introduces wafer-scale fabrication of memristor arrays with CVD- grown hexagonal boron nitride (h-BN) as the active switching layer. This work establishes the multi-state analog pulse programmability and presents the first experimental demonstration of dot-product computation and implementation of multi-variable stochastic linear regression on h-BN memristor hardware. This work extends beyond previous demonstrations of non-volatile resistive switching (NVRS) behavior in isolated h-BN memristors and paves the way for more sophisticated demonstrations of machine learning applications based on 2DMs.
Finally, combining the benefits of CVD-grown 2DMs and graphene edge contacts, vertical h-BN memristors with ultra-small active areas are introduced through this research. These devices achieve low operating currents (high resistance), large RHRS/RLRS ratio, and enable three-dimensional (3D) integration (vertical stacking) for ultimate RRAM scalability. Moreover, they facilitate studying fundamental NVRS mechanisms of single conductive nano-filaments (CNFs) which was previously unattainable in planar devices. This way, single quantum step in conductance was experimentally observed, consistent with theorized atomically-constrained CNFs behavior associated with potential improvements in stability of NVRS operation. This is supported by measured improvements in retention of quantized conductance compared to other non-2DMs filamentary-based memristors.
ContributorsXie, Jing (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Fu, Houqiang (Committee member) / Kozicki, Michael (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2023
Description
This paper delves into the carbon footprint generated by AI chips during their training and operational phases. It highlights the often-overlooked environmental impact of training AI models like ChatGPT, emphasizing the significant CO2 emissions and computational demands involved. The paper also explores the paradoxical nature of AI, which, while contributing to climate change, also holds potential in combating its effects. This dual role of AI sparks ethical debates, particularly concerning strategies to minimize the carbon emissions associated with AI training. Some potential solutions, such as increased transparency among AI-utilizing companies and the adoption of analog-in-memory computing, to address these challenges while also continuing to push the boundaries of AI computing.
ContributorsMulvey, Nicole (Author) / Marinella, Matthew (Thesis director) / Short, Jesse (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2023-12