Matching Items (78)
Description
Wireless video sensor networks has been examined and evaluated for wide range
of applications comprising of video surveillance, video tracking, computer vision, remote
live video and control. The reason behind importance of sensor nodes is its ease
of implementation, ability to operate in adverse environments, easy to troubleshoot,
repair and the high performance level. The biggest challenges with the architectural
design of wireless video sensor networks are power consumption, node failure,
throughput, durability and scalability. The whole project here is to create a gateway
node to integrate between "Internet of things" framework and wireless sensor network.
Our Flexi-Wireless Video Sensor Node Platform (WVSNP) is a low cost, low
power and compatible with traditional sensor network where the main focus was on
maximizing throughput or minimizing node deployment. My task here in this project
was to address the challenges of video power consumption for wireless video sensor
nodes. While addressing the challenges, I performed analysis of predicting the nodes
durability when it is battery operated and to choose appropriate design parameters.
I created a small optimized image to boot up Wandboard DUAL/QUAD board, capture
videos in small/big chunks from the board. The power analysis was performed
for only capturing scenarios, playback of reference videos and, live capturing and realtime
playing of videos on WVSNP player. Each sensor node in sensor network are
battery operated and runs without human intervention. Thus to predict nodes durability,
for dierent video size and format, I have collected power consumption results
and based on this I have provided some recommendation of HW/SW architecture.
i
of applications comprising of video surveillance, video tracking, computer vision, remote
live video and control. The reason behind importance of sensor nodes is its ease
of implementation, ability to operate in adverse environments, easy to troubleshoot,
repair and the high performance level. The biggest challenges with the architectural
design of wireless video sensor networks are power consumption, node failure,
throughput, durability and scalability. The whole project here is to create a gateway
node to integrate between "Internet of things" framework and wireless sensor network.
Our Flexi-Wireless Video Sensor Node Platform (WVSNP) is a low cost, low
power and compatible with traditional sensor network where the main focus was on
maximizing throughput or minimizing node deployment. My task here in this project
was to address the challenges of video power consumption for wireless video sensor
nodes. While addressing the challenges, I performed analysis of predicting the nodes
durability when it is battery operated and to choose appropriate design parameters.
I created a small optimized image to boot up Wandboard DUAL/QUAD board, capture
videos in small/big chunks from the board. The power analysis was performed
for only capturing scenarios, playback of reference videos and, live capturing and realtime
playing of videos on WVSNP player. Each sensor node in sensor network are
battery operated and runs without human intervention. Thus to predict nodes durability,
for dierent video size and format, I have collected power consumption results
and based on this I have provided some recommendation of HW/SW architecture.
i
ContributorsShah, Tejas (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management circuits is the measurement of their frequency response for stability assessment. The standard techniques used in production test environment require expensive measurement equipment (Network Analyzer) and time. These two issues of component variations and frequency response measurement can be addressed if the frequency response of the power converter is used as measure of component (capacitor and inductor) variations. So, a single solution of frequency response measurement solves both the issues. This work examines system identification (frequency response measurement) of power management circuits based on cross correlation technique and proposes the use of switched capacitor correlator for this purpose. A switched capacitor correlator has been designed and used in the system identification of Linear and Switching regulators. The obtained results are compared with the standard frequency response measurement methods of power converters.
ContributorsMalladi, Venkata Naga Koushik (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
ContributorsJavidahmadabadi, Mahdi (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2015
Description
RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed.
In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.
In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.
ContributorsGangula, Sudheer Kumar Reddy (Author) / Kitchen, Jennifer (Thesis advisor) / Ozev, Sule (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced.
Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method.
Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed.
Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.
ContributorsJeong, Jae Woong (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system.
Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems.
The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.
Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems.
The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.
ContributorsAyati, Seyyed Amir (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Bliss, Daniel (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2017
Description
A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi = 2V and Vo = 1.6V.
ContributorsSun, Ming (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Seo, Jae-Sun (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2017
Description
The growing demand for high performance and power hungry portable electronic devices has resulted in alarmingly serious thermal concerns in recent times. The power management system of such devices has thus become increasingly more vital. An integral component of this system is a Low-Dropout Regulator (LDO) which inherently generates a low-noise power supply. Such power supplies are crucial for noise sensitive analog blocks like analog-to-digital converters, phase locked loops, radio-frequency circuits, etc. At higher output power however, a single LDO suffers from increased heat dissipation leading to thermal issues.
This research presents a novel approach to equally and accurately share a large output load current across multiple parallel LDOs to spread the dissipated heat uniformly. The proposed techniques to achieve a high load sharing accuracy of 1% include an innovative fully-integrated accurate current sensing technique based on Dynamic Element Matching and an integrator based servo loop with a low offset feedback amplifier. A novel compensation scheme based on a switched capacitor resistor is referenced to address the high 2A output current specification per LDO across an output voltage range of 1V to 3V. The presented scheme also reduces stringent requirements on off-chip board traces and number of off-chip components thereby making it suitable for portable hand-held systems. The proposed approach can theoretically be extended to any number of parallel LDOs increasing the output current range extensively. The designed load sharing LDO features fast transient response for a low quiescent current consumption of 300µA with a power-supply rejection of 60.7dB at DC. The proposed load sharing technique is verified through extensive simulations for various sources and ranges of mismatch across process, voltage and temperature.
This research presents a novel approach to equally and accurately share a large output load current across multiple parallel LDOs to spread the dissipated heat uniformly. The proposed techniques to achieve a high load sharing accuracy of 1% include an innovative fully-integrated accurate current sensing technique based on Dynamic Element Matching and an integrator based servo loop with a low offset feedback amplifier. A novel compensation scheme based on a switched capacitor resistor is referenced to address the high 2A output current specification per LDO across an output voltage range of 1V to 3V. The presented scheme also reduces stringent requirements on off-chip board traces and number of off-chip components thereby making it suitable for portable hand-held systems. The proposed approach can theoretically be extended to any number of parallel LDOs increasing the output current range extensively. The designed load sharing LDO features fast transient response for a low quiescent current consumption of 300µA with a power-supply rejection of 60.7dB at DC. The proposed load sharing technique is verified through extensive simulations for various sources and ranges of mismatch across process, voltage and temperature.
ContributorsTalele, Bhushan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2017