Matching Items (45)
Description
A photovoltaic (PV) module is a series and parallel connection of multiple PV cells; defects in any cell can cause module power to drop. Similarly, a photovoltaic system is a series and parallel connection of multiple modules, and any low-performing module in the PV system can decrease the system output power. Defects in a solar cell include, but not limited to, the presence of cracks, potential induced degradation (PID), delamination, corrosion, and solder bond degradation. State-of-the-art characterization techniques to identify the defective cells in a module and defective module in a string are i) Current-voltage (IV) curve tracing, ii) Electroluminescence (EL) imaging, and iii) Infrared (IR) imaging. Shortcomings of these techniques include i) unsafe connection and disconnection need to be made with high voltage electrical cables, and ii) labor and time intensive disconnection of the photovoltaic strings from the system.This work presents a non-contact characterization technique to address the above two shortcomings. This technique uses a non-contact electrostatic voltmeter (ESV) along with a probe sensor to measure the surface potential of individual solar cells in a commercial module and the modules in a string in both off-grid and grid-connected systems. Unlike the EL approach, the ESV setup directly measures the surface potential by sensing the electric field lines that are present on the surface of the solar cell.
The off-grid testing of ESV on individual cells and multicells in crystalline silicon (c-Si) modules and on individual cells in cadmium telluride (CdTe) modules and individual modules in a CdTe string showed less than 2% difference in open circuit voltage compared to the voltmeter values. In addition, surface potential mapping of the defective cracked cells in a multicell module using ESV identified the dark, grey, and bright areas of EL images precisely at the exact locations shown by the EL characterization.
The on-grid testing of ESV measured the individual module voltages at maximum power point (Vmpp) and quantitatively identified the exact PID-affected module in the entire system. In addition, the poor-performing non-PID modules of a grid-connected PV system were also identified using the ESV technique.
ContributorsRaza, Hamza Ahmad (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Hacke, Peter (Committee member) / Arizona State University (Publisher)
Created2023
Description
The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
ContributorsKrishnan Achary, Kiran Kumar (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2015
Description
A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
ContributorsMahmoudidaryan, Parisa (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Mehdizad Taleie, Shahin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019