Matching Items (43)

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The Applicability of an Athletic Shoe Comprising an In-Shoe Force Measurement System

Description

Having the proper biomechanical and neuromuscular kinematics while performing an athletic motion is essential for athletes. Deviations from proper form in execution of the kinetic chain of an athletic movement

Having the proper biomechanical and neuromuscular kinematics while performing an athletic motion is essential for athletes. Deviations from proper form in execution of the kinetic chain of an athletic movement may result in suboptimal performance and oftentimes an elevated likelihood of injury. The solutions currently available to athletes to account for digression from proper form are limited to sight and feel analysis of movement by the athletes and coaches and basic medical and athletic analysis equipment that is unsuitable for real-time analysis, the rigor and speed of dynamic athletic motions, and in-field use. The solution proposed herein is one of an in-shoe force measurement and foot positioning system designed to measure the ground reaction force generated by and alignment of an athlete's feet during an athletic motion. Research into various sports has found that the feet play a foundational role in proper execution of the kinetic chain, wherein the alignment, positioning, force generation, and timing of the feet may dictate proper execution of subsequent segments in the kinetic chain. The goal of the present design is to provide athletes with a solution to allow for real-time kinematic analysis of athletic motions using an in-shoe force measurement and foot positioning system. An understanding into the compensatory effect of foot misalignment, mismatched timing, and under or overcompensated ground reaction force generation by the feet on ensuing segments of the kinetic chain in conjunction with the present design can allow for athletes to measure and determine their degree of accuracy in form execution and to predict potential injuries resulting from deviations in form. Our design of an athletic shoe comprising an in-shoe force measurement system provides a dynamic solution to sports-related injuries presently unavailable to athletes.

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Created

Date Created
  • 2017-05

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A fast settling oversampled digital sliding-mode controller for DC-DC buck converters

Description

Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An

Sliding-Mode Control (SMC) has several benefits over traditional Proportional-Integral-Differential (PID) control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. An All-Digital Sliding-Mode (ADSM) controlled DC-DC converter, utilizing single-bit oversampled frequency domain digitizers is proposed. In the proposed approach, feedback and reference digitizing Analog-to-Digital Converters (ADC) are based on a single-bit, first order Sigma-Delta frequency to digital converter, running at 32MHz over-sampling rate. The ADSM regulator achieves 1% settling time in less than 5uSec for a load variation of 600mA. The sliding-mode controller utilizes a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady state error (or DC offset), and limits the switching frequency range, which are the two common problems associated with sliding-mode controllers. The IC is designed and fabricated on a 0.35um CMOS process occupying an active area of 2.72mm-squared. Measured peak efficiency is 83%.

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Created

Date Created
  • 2013

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Single-inductor, dual-input CCM boost converter for multi-junction PV energy harvesting

Description

This thesis presents a power harvesting system combining energy from sub-cells of

multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost

converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor

This thesis presents a power harvesting system combining energy from sub-cells of

multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost

converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current

regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A

modified hill-climbing algorithm is implemented to achieve maximum power point

tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V

output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of

65mW. Measured results show that the peak efficiency achieved is around 85%. The

power switches and control circuits are implemented in standard 0.18um CMOS process.

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Created

Date Created
  • 2017

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A Truly In-shoe Force Measurement System

Description

In this work, the development of a novel and a truly in-shoe force measurement system is reported. The device consists of a shoe insole with six thin film piezoresistive sensors

In this work, the development of a novel and a truly in-shoe force measurement system is reported. The device consists of a shoe insole with six thin film piezoresistive sensors and the main circuit board. The piezoresistive sensors are used for the measurement of plantar pressure during daily human activities. The motion sensor mounted on the main circuit board captures kinematic data. In addition, the main circuit board is responsible for the wireless transmission of the data from all the sensors in real-time using BLE protocol. It is housed within the midsole of the shoe, under the medial arch of the foot. The real-time quantitative data and its analyses, enables athletic performance evaluation, biomedical ailment detection, and everyday fitness tracking. A test subject walked 20 steps on a flat surface at a comfortable speed wearing a shoe fitted with the insole and the main circuit board. Measurements were captured using a BLE enabled laptop and the test results were validated for accuracy. From the real-time data captured, the number of steps walked, the speed and the plantar pressure applied can be clearly established. Moreover, additional kinematic data from the motion sensor was captured. Further processing of kinematic data using techniques such as machine learning is essential to get meaningful inferences.

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Created

Date Created
  • 2018

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High-Efficiency Doherty-Based Power Amplifiers Using GaN Technology For Wireless Infrastructure Applications

Description

The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power

The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.

Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.

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Created

Date Created
  • 2018

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Photovoltaic sub-module integrated converter analysis

Description

With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on

With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.

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Created

Date Created
  • 2012

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A 280 mW, 0.07 % THD+N class-D audio amplifier using a frequency-domain quantizer

Description

Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations

Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.

Contributors

Agent

Created

Date Created
  • 2011

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Medical implant receiver system

Description

The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very

The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. This metric is useful, but incomplete in that it ignores Sensitivity level, bit error rate, and immunity to interferers. In this study exploration of receiver architectures and convergence upon a comprehensive solution is done. This analysis is used to design and build a system for validation. The Direct Conversion Receiver architecture implemented for the MICS standard in 0.18 µm CMOS process consumes approximately 2 mW is competitive with published research.

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Created

Date Created
  • 2012

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CMOS integrated power amplifiers for RF reconfigurable and digital transmitters

Description

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:

1) A transformer-based power combiner architecture for out-phasing transmitters

2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)

3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters

This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.

The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.

Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.

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Created

Date Created
  • 2019

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Hybrid Envelope Tracking Supply Modulator Analysis and Design for Wideband Applications

Description

A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level

A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of

over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-

put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.

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Agent

Created

Date Created
  • 2019