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Description
Parkinson's disease is a neurodegenerative condition diagnosed on patients with

clinical history and motor signs of tremor, rigidity and bradykinesia, and the estimated

number of patients living with Parkinson's disease around the world is seven

to ten million. Deep brain stimulation (DBS) provides substantial relief of the motor

signs of Parkinson's disease patients. It

Parkinson's disease is a neurodegenerative condition diagnosed on patients with

clinical history and motor signs of tremor, rigidity and bradykinesia, and the estimated

number of patients living with Parkinson's disease around the world is seven

to ten million. Deep brain stimulation (DBS) provides substantial relief of the motor

signs of Parkinson's disease patients. It is an advanced surgical technique that is used

when drug therapy is no longer sufficient for Parkinson's disease patients. DBS alleviates the motor symptoms of Parkinson's disease by targeting the subthalamic nucleus using high-frequency electrical stimulation.

This work proposes a behavior recognition model for patients with Parkinson's

disease. In particular, an adaptive learning method is proposed to classify behavioral

tasks of Parkinson's disease patients using local field potential and electrocorticography

signals that are collected during DBS implantation surgeries. Unique patterns

exhibited between these signals in a matched feature space would lead to distinction

between motor and language behavioral tasks. Unique features are first extracted

from deep brain signals in the time-frequency space using the matching pursuit decomposition

algorithm. The Dirichlet process Gaussian mixture model uses the extracted

features to cluster the different behavioral signal patterns, without training or

any prior information. The performance of the method is then compared with other

machine learning methods and the advantages of each method is discussed under

different conditions.
ContributorsDutta, Arindam (Author) / Papandreou-Suppappola, Antonia (Thesis advisor) / Holbert, Keith E. (Committee member) / Bliss, Daniel W. (Committee member) / Arizona State University (Publisher)
Created2015
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Description
The subject of this thesis is distribution level load management using a pricing signal in a smart grid infrastructure. The project relates to energy management in a spe-cialized distribution system known as the Future Renewable Electric Energy Delivery and Management (FREEDM) system. Energy management through demand response is one of

The subject of this thesis is distribution level load management using a pricing signal in a smart grid infrastructure. The project relates to energy management in a spe-cialized distribution system known as the Future Renewable Electric Energy Delivery and Management (FREEDM) system. Energy management through demand response is one of the key applications of smart grid. Demand response today is envisioned as a method in which the price could be communicated to the consumers and they may shift their loads from high price periods to the low price periods. The development and deployment of the FREEDM system necessitates controls of energy and power at the point of end use.

In this thesis, the main objective is to develop the control model of the Energy Management System (EMS). The energy and power management in the FREEDM system is digitally controlled therefore all signals containing system states are discrete. The EMS is modeled as a discrete closed loop transfer function in the z-domain. A breakdown of power and energy control devices such as EMS components may result in energy con-sumption error. This leads to one of the main focuses of the thesis which is to identify and study component failures of the designed control system. Moreover, H-infinity ro-bust control method is applied to ensure effectiveness of the control architecture. A focus of the study is cyber security attack, specifically bad data detection in price. Test cases are used to illustrate the performance of the EMS control design, the effect of failure modes and the application of robust control technique.

The EMS was represented by a linear z-domain model. The transfer function be-tween the pricing signal and the demand response was designed and used as a test bed. EMS potential failure modes were identified and studied. Three bad data detection meth-odologies were implemented and a voting policy was used to declare bad data. The run-ning mean and standard deviation analysis method proves to be the best method to detect bad data. An H-infinity robust control technique was applied for the first time to design discrete EMS controller for the FREEDM system.
ContributorsMusani, Aatif (Author) / Heydt, Gerald (Thesis advisor) / Ayyanar, Raja (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Due to increasing integration of renewable resources in the power grid, an efficient high power transmission system is needed in the near future to transfer energy from remote locations to the load centers. Gas Insulated Transmission Line (GIL) is a specialized high power transmission system, designed by Siemens, for applications

Due to increasing integration of renewable resources in the power grid, an efficient high power transmission system is needed in the near future to transfer energy from remote locations to the load centers. Gas Insulated Transmission Line (GIL) is a specialized high power transmission system, designed by Siemens, for applications requiring direct burial or vertical installation of the transmission line. GIL uses SF6 as an insulating medium. Due to unavoidable gas leakages and high global warming potential of SF6, there is a need to replace this insulating gas by some other possible alternative. Insulating foam materials are characterized by excellent dielectric properties as well as their reduced weight. These materials can find their application in GIL as high voltage insulators. Syntactic foam is a polymer based insulating foam. It consists of a large number of microspheres embedded in a polymer matrix.

The work in this thesis deals with the development of the selection proce-dure for an insulating foam for its application in GIL. All the steps in the process are demonstrated considering syntactic foam as an insulator. As the first step of the procedure, a small representative model of the insulating foam is built in COMSOL Multiphysics software with the help of AutoCAD and Excel VBA to analyze electric field distribution for the application of GIL. The effect of the presence of metal particles on the electric field distribution is also observed. The AC voltage withstand test is performed on the insulating foam samples according to the IEEE standards. The effect of the insulating foam on electrical parameters as well as transmission characteristics of the line is analyzed as the last part of the thesis. The results from all the simulations and AC voltage withstand test are ob-served to predict the suitability of the syntactic foam as an insulator in GIL.
ContributorsPendse, Harshada Ganesh (Author) / Karady, George G. (Thesis advisor) / Holbert, Keith E. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2014
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Description
The space environment comprises cosmic ray particles, heavy ions and high energy electrons and protons. Microelectronic circuits used in space applications such as satellites and space stations are prone to upsets induced by these particles. With transistor dimensions shrinking due to continued scaling, terrestrial integrated circuits are also increasingly susceptible

The space environment comprises cosmic ray particles, heavy ions and high energy electrons and protons. Microelectronic circuits used in space applications such as satellites and space stations are prone to upsets induced by these particles. With transistor dimensions shrinking due to continued scaling, terrestrial integrated circuits are also increasingly susceptible to radiation upsets. Hence radiation hardening is a requirement for microelectronic circuits used in both space and terrestrial applications.

This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.

A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.

A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.

Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
ContributorsShambhulingaiah, Sandeep (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae sun (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies

Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and

Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description or simulation of the design against the RTL implementation. Formal techniques exhaustively analyze parts of the design but, do not verify RTL against the architecture specification. The focus of this work is to implement a fully automated validation environment for a MIPS based radiation hardened microprocessor using simulation based approaches. The basic framework uses the classical validation approach in which the design to be validated is described in a Hardware Definition Language (HDL) such as VHDL or Verilog. To implement a simulation based approach a number of random or pseudo random tests are generated. The output of the HDL based design is compared against the one obtained from a "perfect" model implementing similar functionality, a mismatch in the results would thus indicate a bug in the HDL based design. Effort is made to design the environment in such a manner that it can support validation during different stages of the design cycle. The validation environment includes appropriate changes so as to support architecture changes which are introduced because of radiation hardening. The manner in which the validation environment is build is highly dependent on the specifications of the perfect model used for comparisons. This work implements the validation environment for two MIPS simulators as the reference model. Two bugs have been discovered in the RTL model, using simulation based approaches through the validation environment.
ContributorsSharma, Abhishek (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated

The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
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Description
The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved

The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
ContributorsMaurya, Satendra Kumar (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Power generation in remote isolated places is a tough problem. Presently, a common source for remote generation is diesel. However, diesel generation is costly and environmental unfriendly. It is promising to replace the diesel generation with some clean and economical generation sources. The concept of renewable generation offers a solution

Power generation in remote isolated places is a tough problem. Presently, a common source for remote generation is diesel. However, diesel generation is costly and environmental unfriendly. It is promising to replace the diesel generation with some clean and economical generation sources. The concept of renewable generation offers a solution to remote generation. This thesis focuses on evaluation of renewable generation penetration in the remote isolated grid. A small town named Coober Pedy in South Australia is set as an example. The first task is to build the stochastic models of solar irradiation and wind speed based on the local historical data. With the stochastic models, generation fluctuations and generation planning are further discussed. Fluctuation analysis gives an evaluation of storage unit size and costs. Generation planning aims at finding the relationships between penetration level and costs under constraint of energy sufficiency. The results of this study provide the best penetration level that makes the minimum energy costs. In the case of Coober Pedy, cases of wind and photovoltaic penetrations are studied. The additional renewable sources and suspended diesel generation change the electricity costs. Results show that in remote isolated grid, compared to diesel generation, renewable generation can lower the energy costs.
ContributorsZhu, Yujia (Author) / Holbert, Keith E. (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel J (Committee member) / Arizona State University (Publisher)
Created2012
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Description
The field of flexible displays and electronics gained a big momentum within the recent years due to their ruggedness, thinness, and flexibility as well as low cost large area manufacturability. Amorphous silicon has been the dominant material used in the thin film transistor industry which could only utilize it as

The field of flexible displays and electronics gained a big momentum within the recent years due to their ruggedness, thinness, and flexibility as well as low cost large area manufacturability. Amorphous silicon has been the dominant material used in the thin film transistor industry which could only utilize it as N type thin film transistors (TFT). Amorphous silicon is an unstable material for low temperature manufacturing process and having only one kind of transistor means high power consumption for circuit operations. This thesis covers the three major researches done on flexible TFTs and flexible electronic circuits. First the characterization of both amorphous silicon TFTs and newly emerging mixed oxide TFTs were performed and the stability of these two materials is compared. During the research, both TFTs were stress tested under various biasing conditions and the threshold voltage was extracted to observe the shift in the threshold which shows the degradation of the material. Secondly, the design of the first flexible CMOS TFTs and CMOS gates were covered. The circuits were built using both inorganic and organic components (for nMOS and pMOS transistors respectively) and functionality tests were performed on basic gates like inverter, NAND and NOR gates and the working results are documented. Thirdly, a novel large area sensor structure is demonstrated under the Electronic Textile project section. This project is based on the concept that all the flexible electronics are flexible in only one direction and can not be used for conforming irregular shaped objects or create an electronic cloth for various applications like display or sensing. A laser detector sensor array is designed for proof of concept and is laid in strips that can be cut after manufacturing and weaved to each other to create a real flexible electronic textile. The circuit designed uses a unique architecture that pushes the data in a single line and reads the data from the same line and compares the signal to the original state to determine a sensor excitation. This architecture enables 2 dimensional addressing through an external controller while eliminating the need for 2 dimensional active matrix style electrical connections between the fibers.
ContributorsKaftanoglu, Korhan (Author) / Allee, David R. (Thesis advisor) / Kozicki, Michael N (Committee member) / Holbert, Keith E. (Committee member) / Kaminski, Jann P (Committee member) / Arizona State University (Publisher)
Created2012