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Description
Machine learning is a powerful tool for processing and understanding the vast amounts of data produced by sensors every day. Machine learning has found use in a wide variety of fields, from making medical predictions through correlations invisible to the human eye to classifying images in computer vision applications. A wide range of machine learning algorithms have been developed to attempt to solve these problems, each with different metrics in accuracy, throughput, and energy efficiency. However, even after they are trained, these algorithms require substantial computations to make a prediction. General-purpose CPUs are not well-optimized to this task, so other hardware solutions have developed over time, including the use of a GPU, FPGA, or ASIC.
This project considers the FPGA implementations of MLP and CNN feedforward. While FPGAs provide significant performance improvements, they come at a substantial financial cost. We explore the options of implementing these algorithms on a smaller budget. We successfully implement a multilayer perceptron that identifies handwritten digits from the MNIST dataset on a student-level DE10-Lite FPGA with a test accuracy of 91.99%. We also apply our trained network to external image data loaded through a webcam and a Raspberry Pi, but we observe lower test accuracy in these images. Later, we consider the requirements necessary to implement a more elaborate convolutional neural network on the same FPGA. The study deems the CNN implementation feasible in the criteria of memory requirements and basic architecture. We suggest the CNN implementation on the same FPGA to be worthy of further exploration.
This project considers the FPGA implementations of MLP and CNN feedforward. While FPGAs provide significant performance improvements, they come at a substantial financial cost. We explore the options of implementing these algorithms on a smaller budget. We successfully implement a multilayer perceptron that identifies handwritten digits from the MNIST dataset on a student-level DE10-Lite FPGA with a test accuracy of 91.99%. We also apply our trained network to external image data loaded through a webcam and a Raspberry Pi, but we observe lower test accuracy in these images. Later, we consider the requirements necessary to implement a more elaborate convolutional neural network on the same FPGA. The study deems the CNN implementation feasible in the criteria of memory requirements and basic architecture. We suggest the CNN implementation on the same FPGA to be worthy of further exploration.
ContributorsLythgoe, Zachary James (Author) / Allee, David (Thesis director) / Hartin, Olin (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2019-12
Description
The purpose of the automated pool system is to keep the chlorine level at a safe, reasonable level, by automatically dispensing chlorine in the pool when needed. This was to help the user upkeep with their pool, and also let the user know the current status of their pool. The project will also include Bluetooth communication, for the user to receive ORP, pH, and temperature sensor values. With these values the user will be instructed what chemical need to be added to their pool in order to keep their pool pH at a comfortable level. The user will also be able to prompt the Bluetooth terminal and receive the current ORP, pH, and temperature values of their pool.
ContributorsClarke-Telfer, Nina Lynore (Author) / Hartin, Olin (Thesis director) / Allee, David (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
This thesis covers the continued development of an automatic water shutoff product developed as a capstone project by students in the college of engineering. The continued development covers the process of setting up a publicly accessible web server along with required server components and creating an Alexa skill for smart home integration.
ContributorsEthington, Timothy (Author) / Hartin, Olin (Thesis director) / Aberle, James (Committee member) / Computer Science and Engineering Program (Contributor) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2020-12
Description
Precise Position, Navigation, and Timing (PNT) is necessary for the functioning of many critical infrastructure sectors relied upon by millions every day. Specifically, precise timing is primarily provided through the Global Positioning System (GPS) and its system of satellites that each house multiple atomic clocks. Without precise timing, utilities such as the internet, the power grid, navigational systems, and financial systems would cease operation. Because oscillator devices experience frequency drift during operation, many systems rely on the precise time provided by GPS to maintain synchronization across the globe. However, GPS signals are particularly susceptible to disruption – both intentional and unintentional – due to their space-based, low-power, and unencrypted nature. It is for these reasons that there is a need to develop a system that can provide an accurate timing reference – one disciplined by a GPS signal – and can also maintain its nominal frequency in scenarios of intermittent GPS availability.
This project considers an accurate timing reference deployed via Field Programmable Gate Array (FPGA) and disciplined by a GPS module. The objective is to implement a timing reference on a DE10-Lite FPGA disciplined by the 1 Pulse-Per-Second (PPS) output of an MTK3333 GPS module. When a signal lock is achieved with GPS, the MTK3333 delivers a pulse input to the FPGA on the leading edge of every second. The FPGA aligns a digital oscillator to this PPS reference, providing a disciplined output signal at a 10 MHz frequency that is maintained in events of intermittent GPS availability. The developed solution is evaluated using a frequency counter disciplined by an atomic clock in addition to an oscilloscope. The findings deem the software solution acceptable with more work needed to debug the hardware solution
ContributorsWitthus, Alexander (Author) / Allee, David (Thesis director) / Hartin, Olin (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2022-05