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- Creators: Prokofiev, Sergey, 1891-1953
Description
Register file (RF) memory is important in low power system on chip (SOC) due to its
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
ContributorsVashishtha, Vinay (Author) / Clark, Lawrence T. (Thesis advisor) / Seo, Jae-Sun (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Flash memories are critical for embedded devices to operate properly but are susceptible to radiation effects, which make flash memory a key factor to improve the reliability of circuitry. This thesis describes the simulation techniques used to analyze and predict total ionizing dose (TID) effects on 90-nm technology Silicon Storage Technology (SST) SuperFlash Generation 3 devices. Silvaco Atlas is used for both device level design and simulation purposes.
The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms.
The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad.
The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad.
The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms.
The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad.
The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad.
ContributorsChen, Yitao (Author) / Holbert, Keith E. (Thesis advisor) / Clark, Lawrence T. (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2016
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)
ContributorsProkofiev, Sergey, 1891-1953 (Composer)