Matching Items (3)

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Predictive Process Design Kits for the 7 nm and 5 nm Technology Nodes

Description

Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short

Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, a realistic finFET based predictive process design kit (PDK) that supports investigation into both circuit and physical design, encompassing all aspects of digital design, for academic use has been unavailable. While the finFET based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification (LVS) and parasitic extraction at the time [3][4]. Consequently, the only available sub 45 nm educational PDKs are the planar CMOS based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) [5][6]. The cell libraries available for those processes are not realistic since they use large cell heights, in contrast to recent industry trends. Additionally, the SRAM rules and cells provided by these PDKs are not realistic. Because finFETs have a 3D structure, which affects transistor density, using planar libraries scaled to sub 22 nm dimensions for research is likely to give poor accuracy.

Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non disclosure agreements (NDAs) are un manageable for large university classes and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures.

This work focuses on the development of realistic PDKs for academic use that overcome these limitations. These PDKs, developed for the N7 and N5 nodes, even before 7 nm and 5 nm processes were available in industry, are thus predictive. The predictions have been based on publications of the continually improving lithography, as well as estimates of what would be available at N7 and N5. For the most part, these assumptions have been accurate with regards to N7, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic.

Contributors

Agent

Created

Date Created
  • 2019

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SST SuperFlash modeling and simulation under ionizing radiation

Description

Flash memories are critical for embedded devices to operate properly but are susceptible to radiation effects, which make flash memory a key factor to improve the reliability of circuitry. This

Flash memories are critical for embedded devices to operate properly but are susceptible to radiation effects, which make flash memory a key factor to improve the reliability of circuitry. This thesis describes the simulation techniques used to analyze and predict total ionizing dose (TID) effects on 90-nm technology Silicon Storage Technology (SST) SuperFlash Generation 3 devices. Silvaco Atlas is used for both device level design and simulation purposes.

The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms.

The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad.

The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad.

Contributors

Agent

Created

Date Created
  • 2016

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Register files for embedded low-power applications including microprocessors

Description

Register file (RF) memory is important in low power system on chip (SOC) due to its

inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which

Register file (RF) memory is important in low power system on chip (SOC) due to its

inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.

Contributors

Agent

Created

Date Created
  • 2014