Matching Items (8)

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Temperature dependent simulation of diamond depleted Schottky PIN diodes

Description

Diamond is considered as an ideal material for high field and high power devices due to its high breakdown field, high lightly doped carrier mobility, and high thermal conductivity. The

Diamond is considered as an ideal material for high field and high power devices due to its high breakdown field, high lightly doped carrier mobility, and high thermal conductivity. The modeling and simulation of diamond devices are therefore important to predict the performances of diamond based devices. In this context, we use Silvaco[superscript ®] Atlas, a drift-diffusion based commercial software, to model diamond based power devices. The models used in Atlas were modified to account for both variable range and nearest neighbor hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond. The models were fit to experimentally reported resistivity data over a wide range of doping concentrations and temperatures. We compare to recent data on depleted diamond Schottky PIN diodes demonstrating low turn-on voltages and high reverse breakdown voltages, which could be useful for high power rectifying applications due to the low turn-on voltage enabling high forward current densities. Three dimensional simulations of the depleted Schottky PIN diamond devices were performed and the results are verified with experimental data at different operating temperatures.

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Date Created
  • 2016-06-08

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Modeling of solid state transformer for the FREEDM system demonstration

Description

The Solid State Transformer (SST) is an essential component in the FREEDM system. This research focuses on the modeling of the SST and the controller hardware in the loop (CHIL)

The Solid State Transformer (SST) is an essential component in the FREEDM system. This research focuses on the modeling of the SST and the controller hardware in the loop (CHIL) implementation of the SST for the support of the FREEDM system demonstration. The energy based control strategy for a three-stage SST is analyzed and applied. A simplified average model of the three-stage SST that is suitable for simulation in real time digital simulator (RTDS) has been developed in this study. The model is also useful for general time-domain power system analysis and simulation. The proposed simplified av-erage model has been validated in MATLAB and PLECS. The accuracy of the model has been verified through comparison with the cycle-by-cycle average (CCA) model and de-tailed switching model. These models are also implemented in PSCAD, and a special strategy to implement the phase shift modulation has been proposed to enable the switching model simulation in PSCAD. The implementation of the CHIL test environment of the SST in RTDS is described in this report. The parameter setup of the model has been discussed in detail. One of the dif-ficulties is the choice of the damping factor, which is revealed in this paper. Also the grounding of the system has large impact on the RTDS simulation. Another problem is that the performance of the system is highly dependent on the switch parameters such as voltage and current ratings. Finally, the functionalities of the SST have been realized on the platform. The distributed energy storage interface power injection and reverse power flow have been validated. Some limitations are noticed and discussed through the simulation on RTDS.

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Created

Date Created
  • 2014

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Developing ohmic contacts to Gallium Nitride for high temperature applications

Description

Gallium Nitride (GaN), being a wide-bandgap semiconductor, shows its advantage over the conventional semiconductors like Silicon and Gallium Arsenide for high temperature applications, especially in the temperature range from 300°C

Gallium Nitride (GaN), being a wide-bandgap semiconductor, shows its advantage over the conventional semiconductors like Silicon and Gallium Arsenide for high temperature applications, especially in the temperature range from 300°C to 600°C. Development of stable ohmic contacts to GaN with low contact resistivity has been identified as a prerequisite to the success of GaN high temperature electronics. The focus of this work was primarily derived from the requirement of an appropriate metal contacts to work with GaN-based hybrid solar cell operating at high temperature.

Alloyed Ti/Al/Ni/Au contact and non-alloyed Al/Au contact were developed to form low-resistivity contacts to n-GaN and their stability at high temperature were studied. The alloyed Ti/Al/Ni/Au contact offered a specific contact resistivity (ρc) of 6×10-6 Ω·cm2 at room temperature measured the same as the temperature increased to 400°C. No significant change in ρc was observed after the contacts being subjected to 400°C, 450°C, 500°C, 550°C, and 600°C, respectively, for at least 4 hours in air. Since several device technology prefer non-alloyed contacts Al/Au metal stack was applied to form the contacts to n-type GaN. An initial ρc of 3×10-4 Ω·cm2, measured after deposition, was observed to continuously reduce under thermal stress at 400°C, 450°C, 500°C, 550°C, and 600°C, respectively, finally stabilizing at 5×10-6 Ω·cm2. Both the alloyed and non-alloyed metal contacts showed exceptional capability of stable operation at temperature as high as 600°C in air with low resistivity ~10-6 Ω·cm2, with ρc lowering for the non-alloyed contacts with high temperatures.

The p-GaN contacts showed remarkably superior ohmic behavior at elevated temperatures. Both ρc and sheet resistance (Rsh) of p-GaN decreased by a factor of 10 as the ambient temperature increased from room temperature to 390°C. The annealed Ni/Au contact showed ρc of 2×10-3 Ω·cm2 at room temperature, reduced to 1.6×10-4 Ω·cm2 at 390°C. No degradation was observed after the contacts being subjected to 450°C in air for 48 hours. Indium Tin Oxide (ITO) contacts, which has been widely used as current spreading layer in GaN-base optoelectronic devices, measured an initial ρc [the resistivity of the ITO/p-GaN interface, since the metal/ITO ρc is negligible] of 1×10-2 Ω·cm2 at room temperature. No degradation was observed after the contact being subjected to 450°C in air for 8 hours.

Accelerated life testing (ALT) was performed to further evaluate the contacts stability at high temperatures quantitatively. The ALT results showed that the annealed Ni/Au to p-GaN contacts is more stable in nitrogen ambient, with a lifetime of 2,628 hours at 450°C which is approximately 12 times longer than that at 450°C in air.

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Date Created
  • 2016

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Polarization and electronic state configuration of III-N surfaces and plasma-enhanced atomic layer deposited dielectric interfaces

Description

GaN and AlGaN have shown great potential in next-generation power and RF electronics. However, these devices are limited by reliability issues such as leakage current and current collapse that result

GaN and AlGaN have shown great potential in next-generation power and RF electronics. However, these devices are limited by reliability issues such as leakage current and current collapse that result from surface and interface states on GaN and AlGaN. This dissertation, therefore, examined these electronic states, focusing on the following two points:

First, the surface electronic state configuration was examined with regards to the polarization bound 1013 charges/cm2 that increases with aluminum content. This large bound charge requires compensation either externally by surface states or internally by the space charge regions as relates to band bending. In this work, band bending was measured after different surface treatments of GaN and AlGaN to determine the effects of specific surface states on the electronic state configuration. Results showed oxygen-terminated N-face GaN, Ga-face GaN, and Ga-face Al0.25Ga0.75N surface were characterized by similar band bending regardless of the polarization bound charge, suggesting a Fermi level pinning state ~0.4-0.8 eV below the conduction band minimum. On oxygen-free Ga-face GaN, Al0.15Ga0.85N, Al0.25Ga0.75N, and Al0.35Ga0.65N, band bending increased slightly with aluminum content and thus did not exhibit the same pinning behavior; however, there was still significant compensating charge on these surfaces (~1013 charges/cm2). This charge is likely related to nitrogen vacancies and/or gallium dangling bonds.

In addition, this wozrk investigated the interface electronic state configuration of dielectric/GaN and AlGaN interfaces with regards to deposition conditions and aluminum content. Specifically, oxygen plasma-enhanced atomic layer deposited (PEALD) was used to deposit SiO2. Growth temperature was shown to influence the film quality, where room temperature deposition produced the highest quality films in terms of electrical breakdown. In addition, the valence band offsets (VBOs) appeared to decrease with the deposition temperature, which likely related to an electric field across the Ga2O3 interfacial layer. VBOs were also determined with respect to aluminum content at the PEALD-SiO2/AlxGa1-xN interface, giving 3.0, 2.9, 2.9, and 2.8 eV for 0%, 15%, 25%, and 35% aluminum content, respectively—with corresponding conduction band offsets of 2.5, 2.2, 1.9, and 1.8 eV. This suggests the largest difference manifests in the conduction band, which is in agreement with the charge neutrality level model.

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Date Created
  • 2015

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Study of CdTe/MgxCd1-xTe double heterostructures and their application in high efficiency solar cells and in luminescence refrigeration

Description

CdTe/MgxCd1-xTe double heterostructures (DHs) have been grown on lattice matched InSb (001) substrates using Molecular Beam Epitaxy. The MgxCd1-xTe layers, which have a wider bandgap and type-I band edge alignment

CdTe/MgxCd1-xTe double heterostructures (DHs) have been grown on lattice matched InSb (001) substrates using Molecular Beam Epitaxy. The MgxCd1-xTe layers, which have a wider bandgap and type-I band edge alignment with CdTe, provide sufficient carrier confinement to CdTe, so that the optical properties of CdTe can be studied. The DH samples show very strong Photoluminescence (PL) intensity, long carrier lifetimes (up to 3.6 μs) and low effective interface recombination velocity at the CdTe/MgxCd1 xTe heterointerface (~1 cm/s), indicating the high material quality. Indium has been attempted as an n-type dopant in CdTe and it is found that the carriers are 100% ionized in the doping range of 1×1016 cm-3 to 1×1018 cm-3. With decent doping levels, long minority carrier lifetime, and almost perfect surface passivation by the MgxCd1-xTe layer, the CdTe/MgxCd1-xTe DHs are applied to high efficiency CdTe solar cells. Monocrystalline CdTe solar cells with efficiency of 17.0% and a record breaking open circuit voltage of 1.096 V have been demonstrated in our group.

Mg0.13Cd0.87Te (1.7 eV), also with high material quality, has been proposed as a current matching cell to Si (1.1 eV) solar cells, which could potentially enable a tandem solar cell with high efficiency and thus lower the electricity cost. The properties of Mg0.13Cd0.87Te/Mg0.5Cd0.5Te DHs and solar cells have been investigated. Carrier lifetime as long as 0.56 μs is observed and a solar cell with 11.2% efficiency and open circuit voltage of 1.176 V is demonstrated.

The CdTe/MgxCd1-xTe DHs could also be potentially applied to luminescence refrigeration, which could be used in vibration-free space applications. Both external luminescence quantum efficiency and excitation-dependent PL measurement show that the best quality samples are almost 100% dominated by radiative recombination, and calculation shows that the internal quantum efficiency can be as high as 99.7% at the optimal injection level (1017 cm-3). External luminescence quantum efficiency of over 98% can be realized for luminescence refrigeration with the proper design of optical structures.

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Date Created
  • 2016

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Modeling and design of GaN high electron mobility transistors and hot electron transistors through Monte Carlo particle-based device simulations

Description

In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and

In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.

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Date Created
  • 2016

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Characterization of interface state in silicon carbide metal oxide semiconductor capacitors

Description

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

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Date Created
  • 2015

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Characterization of Plasma-Enhanced Atomic Layer Deposited Ga2O3 using Ga(acac)3 On GaN

Description

This research has studied remote plasma enhanced atomic layer deposited Ga2O3 thin films with gallium acetylacetonate (Ga(acac)3) as Ga precursor and remote inductively coupled oxygen plasma as oxidizer. The Ga2O3

This research has studied remote plasma enhanced atomic layer deposited Ga2O3 thin films with gallium acetylacetonate (Ga(acac)3) as Ga precursor and remote inductively coupled oxygen plasma as oxidizer. The Ga2O3 thin films were mainly considered as passivation layers on GaN. Growth conditions including Ga(acac)3 precursor pulse time, O2 plasma pulse time, N2 purge time and deposition temperature were investigated and optimized on phosphorus doped Si (100) wafer to achieve a saturated self-limiting growth. A temperature growth window was observed between 150 ℃ and 320 ℃. Ga precursor molecules can saturate on the substrate surface in 0.6 s in one cycle and the plasma power saturates at 150 W. A growth rate of 0.31 Å/cycle was observed for PEALD Ga2O3. Since the study is devoted towards Ga2O3 working as passivation layer on GaN, the band alignment of Ga2O3 on GaN were further determined with X-ray Photoemission Spectroscopy and Ultraviolet Photoemission Spectroscopy. Two models are often used to decide the band alignment of a heterojunction: the electron affinity model assumes the heterojunction aligns at the vacuum level, and the charge neutrality level model (CNL) which considers the presence of an interface dipole. The conduction band offset (CBO), valence band offset (VBO) and band bending (BB) of PEALD Ga2O3 thin films on GaN were 0.1 ±0.2 eV, 1.0±0.2 eV and 0.3 eV respectively. Type-I band alignments were determined. Further study including using PEALD Ga2O3 as passivation layer on GaN MOS gate and applying atomic layer etching to GaN was described.

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Created

Date Created
  • 2018