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- Creators: Barrett, The Honors College
Description
With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to aggressive architectural changes for on-chip power management and rapid development to energy efficient hardware accelerators. Accordingly, the objective of this research work is to facilitate software developers to leverage these hardware techniques and improve energy efficiency of the system. To achieve this, I propose two solutions for Linux kernel: Optimal use of these architectural enhancements to achieve greater energy efficiency requires accurate modeling of processor power consumption. Though there are many models available in literature to model processor power consumption, there is a lack of such models to capture power consumption at the task-level. Task-level energy models are a requirement for an operating system (OS) to perform real-time power management as OS time multiplexes tasks to enable sharing of hardware resources. I propose a detailed design methodology for constructing an architecture agnostic task-level power model and incorporating it into a modern operating system to build an online task-level power profiler. The profiler is implemented inside the latest Linux kernel and validated for Intel Sandy Bridge processor. It has a negligible overhead of less than 1\% hardware resource consumption. The profiler power prediction was demonstrated for various application benchmarks from SPEC to PARSEC with less than 4\% error. I also demonstrate the importance of the proposed profiler for emerging architectural techniques through use case scenarios, which include heterogeneous computing and fine grained per-core DVFS. Along with architectural enhancement in general purpose processors to improve energy efficiency, hardware accelerators like Coarse Grain reconfigurable architecture (CGRA) are gaining popularity. Unlike vector processors, which rely on data parallelism, CGRA can provide greater flexibility and compiler level control making it more suitable for present SoC environment. To provide streamline development environment for CGRA, I propose a flexible framework in Linux to do design space exploration for CGRA. With accurate and flexible hardware models, fine grained integration with accurate architectural simulator, and Linux memory management and DMA support, a user can carry out limitless experiments on CGRA in full system environment.
ContributorsDesai, Digant Pareshkumar (Author) / Vrudhula, Sarma (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2013
Description
Although anxiety may be developmentally appropriate, it can become problematic in some youth. From an ecological perspective, social systems, like family and friendships, are theorized to influence developmental trajectories toward (mal)adjustment, but empirical evidence is scant with regard to the relative impact of subjective satisfaction with family and friendship on anxiety problem development. This thesis study used a subsample of approximately 50% Hispanic/Latino clinic-referred youth (n = 71, ages 6-16 years). Overall, results suggest that the effect of friendship satisfaction on anxiety varied as a function of age but not ethnicity, such that there was a significant negative relationship between child-reported friendship satisfaction and anxiety levels for older children (approx. 9 years and older) but not for younger children. The effect of family satisfaction on anxiety also varied as a function of age, such that older children showed a positive relation between child reported family satisfaction and parent reported anxiety. Furthermore, a positive relation between family satisfaction and anxiety was found only for the H/L children. Post hoc analyses regarding cultural underpinnings of this finding and implications for future research are discussed, as are the results regarding differences between parent and child reports of anxiety.
ContributorsHumphrey, Julia (Author) / Pina, Armando A (Thesis advisor) / Doane, Leah (Committee member) / Bradley, Robert (Committee member) / Arizona State University (Publisher)
Created2013
Description
Rapid technology scaling, the main driver of the power and performance improvements of computing solutions, has also rendered our computing systems extremely susceptible to transient errors called soft errors. Among the arsenal of techniques to protect computation from soft errors, Control Flow Checking (CFC) based techniques have gained a reputation of effective, yet low-cost protection mechanism. The basic idea is that, there is a high probability that a soft-fault in program execution will eventually alter the control flow of the program. Therefore just by making sure that the control flow of the program is correct, significant protection can be achieved. More than a dozen techniques for CFC have been developed over the last several decades, ranging from hardware techniques, software techniques, and hardware-software hybrid techniques as well. Our analysis shows that existing CFC techniques are not only ineffective in protecting from soft errors, but cause additional power and performance overheads. For this analysis, we develop and validate a simulation based experimental setup to accurately and quantitatively estimate the architectural vulnerability of a program execution on a processor micro-architecture. We model the protection achieved by various state-of-the-art CFC techniques in this quantitative vulnerability estimation setup, and find out that software only CFC protection schemes (CFCSS, CFCSS+NA, CEDA) increase system vulnerability by 18% to 21% with 17% to 38% performance overhead. Hybrid CFC protection (CFEDC) increases vulnerability by 5%, while the vulnerability remains almost the same for hardware only CFC protection (CFCET); notwithstanding the hardware overheads of design cost, area, and power incurred in the hardware modifications required for their implementations.
ContributorsRhisheekesan, Abhishek (Author) / Shrivastava, Aviral (Thesis advisor) / Colbourn, Charles Joseph (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2013
Description
Despite the compelling nature of goodness of fit and widespread recognition of the concept, empirical support has lagged, potentially due to complexities inherent in measuring such a complicated, relational construct. The present study examined two approaches to measuring goodness of fit in mother-child dyads and prospectively explored associations to mother-child relationship quality, child behavior problems, and parenting stress across the preschool period. In addition, as goodness of fit might be particularly important for children with developmental delays, child developmental risk status was considered as a moderator of goodness of fit processes. Children with (n = 110) and without (n = 137) developmental delays and their mothers were coded while interacting during a number of lab tasks at child age 36 months and during naturalistic home observations at child age 48 months. Mothers and father completed questionnaires at child ages 36 and 60 months assessing child temperamental characteristics, child behavior problems, and parenting stress. Results highlight child-directed effects on mother-child goodness of fit processes across the early child developmental period. Although there was some evidence that mother-child goodness of fit was associated with parenting stress 2 years later, goodness of fit remains an elusive concept. More precise models and expanded developmental perspectives are needed in order to fully capture the transactional and dynamic nature of goodness of fit in the parent-child relationship.
ContributorsNewland, Rebecca Pauline (Author) / Crnic, Keith (Thesis advisor) / Bradley, Robert (Committee member) / Jahromi, Laudan (Committee member) / Millsap, Roger (Committee member) / Arizona State University (Publisher)
Created2014
Description
Stream computing has emerged as an importantmodel of computation for embedded system applications particularly in the multimedia and network processing domains. In recent past several programming languages and embedded multi-core processors have been proposed for streaming applications. This thesis examines the execution and dynamic scheduling of stream programs on embedded multi-core processors. The thesis addresses the problem in the context of a multi-tasking environment with a time varying allocation of processing elements for a particular streaming application. As a solution the thesis proposes a two step approach where the stream program is compiled to gather key application information, and to generate re-targetable code. A light weight dynamic scheduler incorporates the second stage of the approach. The dynamic scheduler utilizes the static information and available resources to assign or partition the application across the multi-core architecture. The objective of the dynamic scheduler is to maximize the throughput of the application, and it is sensitive to the resource (processing elements, scratch-pad memory, DMA bandwidth) constraints imposed by the target architecture. We evaluate the proposed approach by compiling and scheduling benchmark stream programs on a representative embedded multi-core processor. We present experimental results that evaluate the quality of the solutions generated by the proposed approach by comparisons with existing techniques.
ContributorsLee, Haeseung (Author) / Chatha, Karamvir (Thesis advisor) / Vrudhula, Sarma (Committee member) / Chakrabarti, Chaitali (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2013
Description
Research regarding social competence is growing rapidly, but there remain a few aspects of social development that merit more attention. The presented pair of studies were planned to address two such areas in the social development literature, specifically the longitudinal trajectories of social competence and the role of social competence in second language development in language minority (LM) students. The goal of the first investigation was to examine the developmental trends of interpersonal skills (IS) across the early childhood and elementary school years in a nationally representative, U.S. sample. The goal of the second study was to examine whether differing trajectories of IS development in language minority children in the U.S. were related to their language and literacy (LL) skills at grade 5. Both studies utilized data from the Early Childhood Longitudinal Study - Kindergarten Class of 1998-1999 and modeled ratings of children's IS at five time points between fall of kindergarten and spring of fifth grade using latent class growth analyses in Mplus. In study 1, the best model was a quadratic two-class latent class growth analysis. Trajectory class 1 was a higher-level path with a marginally significant non-linear shape and class 2 was a primarily stable, moderate level path with a slight, non-significant increase over time. The same pattern of results emerged for both boys and girls separately as with the combined-sex model, and in all three final models the proportion of the sample in the higher-level class was greater than the moderate-level class. In study 2 a sample of U.S. children whose primary language at home was something other than English was utilized. LL at the start of kindergarten and sex were included as covariates and LL in fifth grade as a distal outcome. The best model for the data was a cubic two-class latent class growth analysis. Class 1 followed a higher-level path with small, incremental change over time and class 2 was a moderate-level path with greater undulation. Both covariates significantly predicted latent class and language and literacy scores at grade 5 differed significantly across classes.
ContributorsDiDonato, Alicia (Author) / Wilcox, M. Jeanne (Thesis advisor) / Bradley, Robert (Committee member) / Wilkens, Natalie (Committee member) / Valiente, Carlos (Committee member) / Arizona State University (Publisher)
Created2014
Description
Coarse-Grained Reconfigurable Architectures (CGRA) are a promising fabric for improving the performance and power-efficiency of computing devices. CGRAs are composed of components that are well-optimized to execute loops and rotating register file is an example of such a component present in CGRAs. Due to the rotating nature of register indexes in rotating register file, it is very challenging, if at all possible, to hold and properly index memory addresses (pointers) and static values. In this Thesis, different structures for CGRA register files are investigated. Those structures are experimentally compared in terms of performance of mapped applications, design frequency, and area. It is shown that a register file that can logically be partitioned into rotating and non-rotating regions is an excellent choice because it imposes the minimum restriction on underlying CGRA mapping algorithm while resulting in efficient resource utilization.
ContributorsSaluja, Dipal (Author) / Shrivastava, Aviral (Thesis advisor) / Lee, Yann-Hang (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2014
Description
This study investigated father-child Activation Theory and the impact of activative fathering on children's dysregulation and social skills. The sample followed 145 families of typically developing children across ages 4 to 6. Fathering and mothering behaviors were coded via naturalistic observations at child age 4, children's dysregulation was coded during a laboratory puzzle task at age 5, and children's social skills were rated by parents and teachers at age 6. Results found support for a constellation of activative fathering behaviors unique to father-child interactions. Activative fathering, net of mothering behaviors, predicted decreased behavioral dysregulation one year later. Support was not found for moderation of the relation between activative fathering and children's dysregulation by paternal warmth, nor was support found for children's dysregulation as a mediator of the relation between activative fathering and children's social skills. These results suggest that parenting elements of father-child activation are unique to fathering and may be more broadly observable in naturalistic contexts not limited to play activities alone. Additionally, activative fathering appears to uniquely influence children's self-regulatory abilities above and beyond identical mothering behavior. In the present work, paternal warmth was not a necessary for activative fathering to positively contribute to children's regulatory abilities nor did children's dysregulation link activative fathering to social skills.
ContributorsStevenson, Matthew (Author) / Crnic, Keith (Thesis advisor) / Dishion, Thomas (Committee member) / Bradley, Robert (Committee member) / Eisenberg, Nancy (Committee member) / Arizona State University (Publisher)
Created2014
Description
The need for multi-core architectural trends was realized in the desktop computing domain fairly long back. This trend is also beginning to be seen in the deeply embedded systems such as automotive and avionics industry owing to ever increasing demands in terms of sheer computational bandwidth, responsiveness, reliability and power consumption constraints. The adoption of such multi-core architectures in safety critical systems is often met with resistance owing to the overhead in migration of the existing stable code base to the new system setup, typically requiring extensive re-design. This also brings about the need for exhaustive testing and validation that goes hand in hand with such a migration, especially in safety critical real-time systems.
This project highlights the steps to develop an asymmetric multiprocessing variant of Micrium µC/OS-II real-time operating system suited for a multi-core system. This RTOS variant also supports multi-core synchronization, shared memory management and multi-core messaging queues.
Since such specialized embedded systems are usually developed by system designers focused more so on the functionality than on the coding standards, the adoption of automatic production code generation tools, such as SIMULINK's Embedded Coder, is increasingly becoming the industry norm. Such tools are capable of producing robust, industry compliant code with very little roll out time. This project documents the process of extending SIMULINK's automatic code generation tool for the AMP variant of µC/OS-II on Freescale's MPC5675K, dual-core Microcontroller Unit. This includes code generation from task based models and multi-rate models. Apart from this, it also de-scribes the development of additional software tools to allow semantically consistent communication between task on the same kernel and those across the kernels.
This project highlights the steps to develop an asymmetric multiprocessing variant of Micrium µC/OS-II real-time operating system suited for a multi-core system. This RTOS variant also supports multi-core synchronization, shared memory management and multi-core messaging queues.
Since such specialized embedded systems are usually developed by system designers focused more so on the functionality than on the coding standards, the adoption of automatic production code generation tools, such as SIMULINK's Embedded Coder, is increasingly becoming the industry norm. Such tools are capable of producing robust, industry compliant code with very little roll out time. This project documents the process of extending SIMULINK's automatic code generation tool for the AMP variant of µC/OS-II on Freescale's MPC5675K, dual-core Microcontroller Unit. This includes code generation from task based models and multi-rate models. Apart from this, it also de-scribes the development of additional software tools to allow semantically consistent communication between task on the same kernel and those across the kernels.
ContributorsBulusu, Girish Rao (Author) / Lee, Yann-Hang (Thesis advisor) / Fainekos, Georgios (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2014
Description
Stream processing has emerged as an important model of computation especially in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and are mainly characterized by real-time constraints that demand high throughput and data bandwidth with limited global data reuse. Conventional architectures fail to meet these demands due to their poorly matched execution models and the overheads associated with instruction and data movements.
This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks architecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. Each instruction in a SE is locked to a Reservation Station (RS) and revitalizes itself after execution; thus never retiring from the RS. The entire kernel is hosted in RS Banks (RSBs) close to functional units for energy-efficient instruction delivery. The dataflow semantics of stream kernels are captured by a context-aware dataflow execution mode that efficiently exploits the Instruction Level Parallelism (ILP) and Data-level parallelism (DLP) within stream kernels.
Multiple SEs are grouped together to form a StreamCluster (SC) that communicate via a local interconnect. A novel software FIFO virtualization technique with split-join functionality is proposed for efficient and scalable stream communication across SEs. The proposed communication mechanism exploits the Task-level parallelism (TLP) of the stream application. The performance and scalability of the communication mechanism is evaluated against the existing data movement schemes for scratchpad based multi-core architectures. Further, overlay schemes and architectural support are proposed that allow hosting any number of kernels on the StreamWorks architecture. The proposed oevrlay schemes for code management supports kernel(context) switching for the most common use cases and can be adapted for any multi-core architecture that use software managed local memories.
The performance and energy-efficiency of the StreamWorks architecture is evaluated for stream kernel and application benchmarks by implementing the architecture in 45nm TSMC and comparison with a low power RISC core and a contemporary accelerator.
This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks architecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. Each instruction in a SE is locked to a Reservation Station (RS) and revitalizes itself after execution; thus never retiring from the RS. The entire kernel is hosted in RS Banks (RSBs) close to functional units for energy-efficient instruction delivery. The dataflow semantics of stream kernels are captured by a context-aware dataflow execution mode that efficiently exploits the Instruction Level Parallelism (ILP) and Data-level parallelism (DLP) within stream kernels.
Multiple SEs are grouped together to form a StreamCluster (SC) that communicate via a local interconnect. A novel software FIFO virtualization technique with split-join functionality is proposed for efficient and scalable stream communication across SEs. The proposed communication mechanism exploits the Task-level parallelism (TLP) of the stream application. The performance and scalability of the communication mechanism is evaluated against the existing data movement schemes for scratchpad based multi-core architectures. Further, overlay schemes and architectural support are proposed that allow hosting any number of kernels on the StreamWorks architecture. The proposed oevrlay schemes for code management supports kernel(context) switching for the most common use cases and can be adapted for any multi-core architecture that use software managed local memories.
The performance and energy-efficiency of the StreamWorks architecture is evaluated for stream kernel and application benchmarks by implementing the architecture in 45nm TSMC and comparison with a low power RISC core and a contemporary accelerator.
ContributorsPanda, Amrit (Author) / Chatha, Karam S. (Thesis advisor) / Wu, Carole-Jean (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2014