My honors thesis took the form of a creative project. My final deliverables are my research presentation (pdf attachment) and solar powered electric scooter (image attachment). The goal of my project was to fix a second-hand electric scooter and create a solar-powered charger for its battery. The research portion of my creative project focused on exploring the circuit elements in a solar charging schematic and their relationships to power output. First, I explored methods of maximizing power output of the basic solar charging schematic. To find the maximum power output based on different settings of photocurrent (sunlight), I wrote a MATLAB code to calculate maximum power based on its derivative with respect to voltage set equal to zero. Finding this maximum power point in MATLAB allowed me to find its corresponding current and voltage output to produce that exact power. With these max current and voltage values, I was able to solve for an ideal resistor value to set in series with the solar panel in order to achieve these values. In doing so, I designed a maximum power point tracker (MPPT). This became an essential component in my charger’s final design. Next, I explored the microcircuit level of a solar panel schematic. In order to do so, I had to break my single diode model into several diodes in series, resulting in the overall solar panel voltage drop (aka the voltage rating of the solar panel) being divided N times. To find what this N value for a given solar panel is, I performed a lab experiment using a small solar panel and a floodlight to gather the panel’s turn on current and open circuit voltage. These two values helped me find the solar panel’s N value after linearizing the lab data. Now, with a much deeper understanding of solar charging circuitry, I was able to move forward with the design and implementation phase. The design and implementation portion of my creative project included the physical assembly of the solar-powered scooter. First, I analyzed the efficiency differences between having an AC coupled vs. DC coupled system. Due to the added complexity of AC conversions, I deemed it unnecessary to use an inverter in the charger. The charging schematic I designed only called for a charge controller and MPPT, both parts that could easily DC couple the system. Keeping the system in DC from solar panel to battery was definitely the most efficient method, so DC coupling was my final selection. Next, I calculated the required current and voltage output of my charger to meet the specs of the battery and the requirements I set for my project. Finally, I designed a solar array based on these ratings. The final design includes one 30 W panel in parallel with two series-connected 5W panels. The two series panels are affixed on the scooter neck for a built in charge design so that the scooter can be charged anywhere (outside while not in use). The big panel can be connected using a parallel branch in the charging cord that I spliced for added current if charging is set up in a stationary setting (by a window at home). The final design serves the need for sustainable micro mobility in a daily 50% depletion use case kept above 20% charged at all times.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.