Matching Items (141)
Description
Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.
ContributorsGummalla, Samatha (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
One of the challenges in future semiconductor device design is excessive rise of power dissipation and device temperatures. With the introduction of new geometrically confined device structures like SOI, FinFET, nanowires and continuous incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. This work examines the degradation in the ON-current due to self-heating effects in 10 nm channel length silicon nanowire transistors. As part of this dissertation, a 3D electrothermal device simulator is developed that self-consistently solves electron Boltzmann transport equation with 3D energy balance equations for both the acoustic and the optical phonons. This device simulator predicts temperature variations and other physical and electrical parameters across the device for different bias and boundary conditions. The simulation results show insignificant current degradation for nanowire self-heating because of pronounced velocity overshoot effect. In addition, this work explores the role of various placement of the source and drain contacts on the magnitude of self-heating effect in nanowire transistors. This work also investigates the simultaneous influence of self-heating and random charge effects on the magnitude of the ON current for both positively and negatively charged single charges. This research suggests that the self-heating effects affect the ON-current in two ways: (1) by lowering the barrier at the source end of the channel, thus allowing more carriers to go through, and (2) via the screening effect of the Coulomb potential. To examine the effect of temperature dependent thermal conductivity of thin silicon films in nanowire transistors, Selberherr's thermal conductivity model is used in the device simulator. The simulations results show larger current degradation because of self-heating due to decreased thermal conductivity . Crystallographic direction dependent thermal conductivity is also included in the device simulations. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction which is in agreement with the values for the thermal conductivity tensor provided by Zlatan Aksamija.
ContributorsHossain, Arif (Author) / Vasileska, Dragica (Thesis advisor) / Ahmed, Shaikh (Committee member) / Bakkaloglu, Bertan (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2011
Description
A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA
ContributorsNaqvi, Syed Roomi (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Chae, Junseok (Committee member) / Barnby, Hugh (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2011
Description
Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.
ContributorsZazzera, Joshua (Author) / Bakkaloglu, Bertan (Thesis advisor) / Song, Hongjiang (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static (QS) description of the MOSFET. The model is implemented in two widely used circuit simulators and tested for speed and convergence. It is verified by comparison with technology computer aided design (TCAD) simulations and experimental data, and by application of a recently developed benchmark test for NQS MOSFET models. In addition, a new and simple technique to characterize NQS and gate resistance, Rgate, MOS model parameters from measured data has been presented. In the process of experimental model verification, the effects of bulk resistance on MOSFET characteristics is investigated both theoretically and experimentally to separate it from the NQS effects.
ContributorsZhu, Zeqin (Author) / Gildenblat, Gennady (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Barnaby, Hugh (Committee member) / Mcandrew, Colin C (Committee member) / Arizona State University (Publisher)
Created2012
Description
Three-dimensional (3D) inductors with square, hexagonal and octagonal geometries have been designed and simulated in ANSYS HFSS. The inductors have been designed on Silicon substrate with through-hole via with different width, spacing and thickness. Spice modeling has been done in Agilent ADS and comparison has been made with results of custom excel based calculator and HFSS simulation results. Single ended quality factor was measured as 12.97 and differential ended quality factor was measured as 15.96 at a maximum operational frequency of 3.65GHz. The single ended and differential inductance was measured as 2.98nH and 2.88nH respectively at this frequency. Based on results a symmetric octagonal inductor design has been recommended to be used for application in RF biosensing. A system design has been proposed based on use of this inductor and principle of inductive sensing using magnetic labeling.
ContributorsAbbey, Hemanshu (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2012
Description
During the last decades the development of the transistor and its continuous down-scaling allowed the appearance of cost effective wireless communication systems. New generation wideband wireless mobile systems demand high linearity, low power consumption and the low cost devices. Traditional RF systems are mainly analog-based circuitry. Contrary to digital circuits, the technology scaling results in reduction on the maximum voltage swing which makes RF design very challenging. Pushing the interface between the digital and analog boundary of the RF systems closer to the antenna becomes an attractive trend for modern RF devices. In order to take full advantages of the deep submicron CMOS technologies and digital signal processing (DSP), there is a strong trend towards the development of digital transmitter where the RF upconversion is part of the digital-to-analog conversion (DAC). This thesis presents a new digital intermediate frequency (IF) to RF transmitter for 2GHz wideband code division multiple access (W-CDMA). The proposed transmitter integrates a 3-level digital IF current-steering cell, an up-conversion mixer with a tuned load and an RF variable gain amplifier (RF VGA) with an embedded finite impulse response (FIR) reconstruction filter in the up-conversion path. A 4th-order 1.5-bit IF bandpass sigma delta modulator (BP SDM) is designed to support in-band SNR while the out-of-band quantization noise due to the noise shaping is suppressed by the embedded reconstruction filter to meet spectrum emission mask and ACPR requirements. The RF VGA provides 50dB power scaling in 10-dB steps with less than 1dB gain error. The design is fabricated in a 0.18um CMOS technology with a total core area of 0.8 x 1.6 mm2. The IC delivers 0dBm output power at 2GHz and it draws approximately 120mA from a 1.8V DC supply at the maximum output power. The measurement results proved that a digital-intensive digital IF to RF converter architecture can be successfully employed for WCDMA transmitter application.
ContributorsHan, Yongping (Author) / Kiaei, Sayfe (Thesis advisor) / Yu, Hongyu (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.
ContributorsGhajar, Mohammad Reza (Author) / Thornton, Trevor (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2012
Description
With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.
ContributorsSen, Sourav (Author) / Ayyanar, Raja (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
Description
Power supply management is important for MEMS (Micro-Electro-Mechanical-Systems) bio-sensing and chemical sensing applications. The dissertation focuses on discussion of accessibility to different power sources and supply tuning in sensing applications. First, the dissertation presents a high efficiency DC-DC converter for a miniaturized Microbial Fuel Cell (MFC). The miniaturized MFC produces up to approximately 10µW with an output voltage of 0.4-0.7V. Such a low voltage, which is also load dependent, prevents the MFC to directly drive low power electronics. A PFM (Pulse Frequency Modulation) type DC-DC converter in DCM (Discontinuous Conduction Mode) is developed to address the challenges and provides a load independent output voltage with high conversion efficiency. The DC-DC converter, implemented in UMC 0.18µm technology, has been thoroughly characterized, coupled with the MFC. At 0.9V output, the converter has a peak efficiency of 85% with 9µW load, highest efficiency over prior publication. Energy could be harvested wirelessly and often has profound impacts on system performance. The dissertation reports a side-by-side comparison of two wireless and passive sensing systems: inductive and electromagnetic (EM) couplings for an application of in-situ and real-time monitoring of wafer cleanliness in semiconductor facilities. The wireless system, containing the MEMS sensor works with battery-free operations. Two wireless systems based on inductive and EM couplings have been implemented. The working distance of the inductive coupling system is limited by signal-to-noise-ratio (SNR) while that of the EM coupling is limited by the coupled power. The implemented on-wafer transponders achieve a working distance of 6 cm and 25 cm with a concentration resolution of less than 2% (4 ppb for a 200 ppb solution) for inductive and EM couplings, respectively. Finally, the supply tuning is presented in bio-sensing application to mitigate temperature sensitivity. The FBAR (film bulk acoustic resonator) based oscillator is an attractive method in label-free sensing application. Molecular interactions on FBAR surface induce mass change, which results in resonant frequency shift of FBAR. While FBAR has a high-Q to be sensitive to the molecular interactions, FBAR has finite temperature sensitivity. A temperature compensation technique is presented that improves the temperature coefficient of a 1.625 GHz FBAR-based oscillator from -118 ppm/K to less than 1 ppm/K by tuning the supply voltage of the oscillator. The tuning technique adds no additional component and has a large frequency tunability of -4305 ppm/V.
ContributorsZhang, Xu (Author) / Chae, Junseok (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Kozicki, Michael (Committee member) / Phillips, Stephen (Committee member) / Arizona State University (Publisher)
Created2012