Matching Items (131)

137253-Thumbnail Image.png

Design of a RF Transmitting Belt as Part of a Wireless SCS System

Description

The belt component of a unique and novel wireless spinal cord stimulator (SCS) system was conceived, designed, made, and verified. This thesis details and documents all work from inception through

The belt component of a unique and novel wireless spinal cord stimulator (SCS) system was conceived, designed, made, and verified. This thesis details and documents all work from inception through preliminary verification and includes recommendations for future work. The purpose, scope, and objectives of the design and the thesis are introduced. Background literature is presented to provide context for the wireless SCS system as well as the belt component of the system. The product development process used to design the product is outlined. Requirements and constraints are determined from customer needs. Design options are considered and the best concept is selected. The design is made, optimized, and verified to meet the requirements. Future work for this design, outside the scope of this thesis, is discussed. Recommendations and conclusions following completion of the design are included as well.

Contributors

Agent

Created

Date Created
  • 2014-05

137671-Thumbnail Image.png

NGExtract 2: MOSFET Parameter Extraction Tool

Description

NGExtract 2 is a complete transistor (MOSFET) parameter extraction solution based upon the original computer program NGExtract by Rahul Shringarpure written in February 2007. NGExtract 2 is written in

NGExtract 2 is a complete transistor (MOSFET) parameter extraction solution based upon the original computer program NGExtract by Rahul Shringarpure written in February 2007. NGExtract 2 is written in Java and based around the circuit simulator NGSpice. The goal of the program is to be used to produce accurate transistor models based around real-world transistor data. The program contains numerous improvements to the original program:
• Completely rewritten with performance and usability in mind
• Cross-Platform vs. Linux Only
• Simple installation procedure vs. compilation and manual library configuration
• Self-contained, single file runtime
• Particle Swarm Optimization routine
NGExtract 2 works by plotting the Ids vs. Vds and Ids vs. Vgs curves of a simulation model and the measured, real-world data. The user can adjust model parameters and re-simulate to attempt to match the curves. The included Particle Swarm Optimization routine attempts to automate this process by iteratively attempting to improve a solution by measuring its sum-squared error against the real-world data that the user has provided.

Contributors

Agent

Created

Date Created
  • 2013-05

Development of Electrical Instrumentation for Multiplexed Diabetes Management

Description

This report outlines the current methods and instrumentation used for diabetes monitoring and detection, and evaluates the problems that these methods face. Additionally, it will present an approach to remedy

This report outlines the current methods and instrumentation used for diabetes monitoring and detection, and evaluates the problems that these methods face. Additionally, it will present an approach to remedy these problems. The purpose of this project is to create a potentiostat that is capable of controlling a diabetes meter that monitors multiple biological markers simultaneously. Glucose is the most commonly measured biomarker for diabetes. However, it provides only a limited amount of information. In order to give the user of the meter more information about the progression of his or her disease, the concentrations of several different biological markers for diabetes may be measured using a system that operates in a similar fashion to blood glucose meters. The potentiostat provides an input voltage into the electrode sensor and receives the current from the sensor as the output. From this information, the impedance may be calculated. The concentrations of each of the biomarkers in the blood sample can then be determined. In an effort to increase sensitivity, the diabetes meter forgoes the use of amperometric i-t in favor of the electrochemical impedance spectroscopy technique. A three-electrode electrochemical sensor is used with the meter. In order to perform simultaneous and rapid testing of biomarker concentration, a single multisine input wave is generated using a hardware implementation of a summing amplifier and waveform generators.

Contributors

Agent

Created

Date Created
  • 2013-05

134177-Thumbnail Image.png

Active Ripple Cancellation in Hysteretic Controlled Buck Converters

Description

Buck converters are a class of switched-mode power converters often used to step down DC input voltages to a lower DC output voltage. These converters naturally produce a current and

Buck converters are a class of switched-mode power converters often used to step down DC input voltages to a lower DC output voltage. These converters naturally produce a current and voltage ripple at their output due to their switching action. Traditional methods of reducing this ripple have involved adding large discrete inductors and capacitors to filter the ripple, but large discrete components cannot be integrated onto chips. As an alternative to using passive filtering components, this project investigates the use of active ripple cancellation to reduce the peak output ripple. Hysteretic controlled buck converters were chosen for their simplicity of design and fast transient response. The proposed cancellation circuits sense the output ripple of the buck converter and inject an equal ripple exactly out of phase with the sensed ripple. Both current-mode and voltage-mode feedback loops are simulated, and the effectiveness of each cancellation circuit is examined. Results show that integrated active ripple cancellation circuits offer a promising substitute for large discrete filters.

Contributors

Agent

Created

Date Created
  • 2017-12

149992-Thumbnail Image.png

An analytical approach to efficient circuit variability analysis in scaled CMOS design

Description

Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations

Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and oxide thickness fluctuation. These variations greatly impact all aspects of circuit performance and pose a grand challenge to future robust IC design. To improve robustness, efficient methodology is required that considers effect of variations in the design flow. Analyzing timing variability of complex circuits with HSPICE simulations is very time consuming. This thesis proposes an analytical model to predict variability in CMOS circuits that is quick and accurate. There are several analytical models to estimate nominal delay performance but very little work has been done to accurately model delay variability. The proposed model is comprehensive and estimates nominal delay and variability as a function of transistor width, load capacitance and transition time. First, models are developed for library gates and the accuracy of the models is verified with HSPICE simulations for 45nm and 32nm technology nodes. The difference between predicted and simulated σ/μ for the library gates is less than 1%. Next, the accuracy of the model for nominal delay is verified for larger circuits including ISCAS'85 benchmark circuits. The model predicted results are within 4% error of HSPICE simulated results and take a small fraction of the time, for 45nm technology. Delay variability is analyzed for various paths and it is observed that non-critical paths can become critical because of Vth variation. Variability on shortest paths show that rate of hold violations increase enormously with increasing Vth variation.

Contributors

Agent

Created

Date Created
  • 2011

149852-Thumbnail Image.png

Aging predictive models and simulation methods for analog and mixed-signal circuits

Description

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient simulation methods are essential for

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient simulation methods are essential for circuit level reliability prediction. This work proposes a set of compact models of NBTI and CHC effects for analog and mixed-signal circuit, and a direct prediction method which is different from conventional simulation methods. This method is applied in circuit benchmarks and evaluated. This work helps with improving efficiency and accuracy of circuit aging prediction.

Contributors

Agent

Created

Date Created
  • 2011

149788-Thumbnail Image.png

A New RNS 4-moduli set for the implementation of FIR filters

Description

Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The critical aspect in the

Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The critical aspect in the application of RNS is the selection of the moduli set and the design of the conversion units. There have been several RNS moduli sets proposed for the implementation of digital filters. However, some are unbalanced and some do not provide the required dynamic range. This thesis addresses the drawbacks of existing RNS moduli sets and proposes a new moduli set for efficient implementation of FIR filters. An efficient VLSI implementation model has been derived for the design of a reverse converter from RNS to the conventional two's complement representation. This model facilitates the realization of a reverse converter for better performance with less hardware complexity when compared with the reverse converter designs of the existing balanced 4-moduli sets. Experimental results comparing multiply and accumulate units using RNS that are implemented using the proposed four-moduli set with the state-of-the-art balanced four-moduli sets, show large improvements in area (46%) and power (43%) reduction for various dynamic ranges. RNS FIR filters using the proposed moduli-set and existing balanced 4-moduli set are implemented in RTL and compared for chip area and power and observed 20% improvements. This thesis also presents threshold logic implementation of the reverse converter.

Contributors

Agent

Created

Date Created
  • 2011

149893-Thumbnail Image.png

Temperature compensated, high common mode range, Cu-trace based current shunt monitors design and analysis

Description

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA to 200mA for the direct current reading topology and from 1mA to 500mA for the indirect current reading topology across a typical board Cu-trace resistance of 1 ohm with less than 10 µV input-referred offset, 0.3 µV/°C offset drift and 0.1% accuracy for both topologies. Proposed systems avoid using a costly zero-temperature coefficient (TC) sense resistor that is normally used in typical CSM systems. Instead, both of the designs used existing Cu-trace on the printed circuit board (PCB) in place of the costly resistor. The systems use chopper stabilization at the front-end amplifier signal path to suppress input-referred offset down to less than 10 µV. Switching current-mode (SI) FIR filtering technique is used at the instrumentation amplifier output to filter out the chopping ripple caused by input offset and flicker noise by averaging half of the phase 1 signal and the other half of the phase 2 signal. In addition, residual offset mainly caused by clock feed-through and charge injection of the chopper switches at the chopping frequency and its multiple frequencies notched out by the since response of the SI-FIR filter. A frequency domain Sigma Delta ADC which is used for the indirect current reading type design enables a digital interface to processor applications with minimally added circuitries to build a simple 1st order Sigma Delta ADC. The CSMs are fabricated on a 0.7µm CMOS process with 3 levels of metal, with maximum Vds tolerance of 8V and operates across a common mode range of 0 to 26V for the direct current reading type and of 0 to 30V for the indirect current reading type achieving less than 10nV/sqrtHz of flicker noise at 100 Hz for both approaches. By using a semi-digital SI-FIR filter, residual chopper offset is suppressed down to 0.5mVpp from a baseline of 8mVpp, which is equivalent to 25dB suppression.

Contributors

Agent

Created

Date Created
  • 2011

150029-Thumbnail Image.png

Fully differential difference amplifier based microphone interface circuit and an adaptive signal to noise ratio analog front end for dual channel digital hearing aids

Description

A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems

A dual-channel directional digital hearing aid (DHA) front-end using a fully differential difference amplifier (FDDA) based Microphone interface circuit (MIC) for a capacitive Micro Electro Mechanical Systems (MEMS) microphones and an adaptive-power analog font end (AFE) is presented. The Microphone interface circuit based on FDDA converts the capacitance variations into voltage signal, achieves a noise of 32 dB SPL (sound pressure level) and an SNR of 72 dB, additionally it also performs single to differential conversion allowing for fully differential analog signal chain. The analog front-end consists of 40dB VGA and a power scalable continuous time sigma delta ADC, with 68dB SNR dissipating 67u¬W from a 1.2V supply. The ADC implements a self calibrating feedback DAC, for calibrating the 2nd order non-linearity. The VGA and power scalable ADC is fabricated on 0.25 um CMOS TSMC process. The dual channels of the DHA are precisely matched and achieve about 0.5dB gain mismatch, resulting in greater than 5dB directivity index. This will enable a highly integrated and low power DHA

Contributors

Agent

Created

Date Created
  • 2011

150106-Thumbnail Image.png

Design of a modified Cherry-Hooper transimpedance amplifier with DC offset cancellation

Description

Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to

Optical receivers have many different uses covering simple infrared receivers, high speed fiber optic communication and light based instrumentation. All of them have an optical receiver that converts photons to current followed by a transimpedance amplifier to convert the current to a useful voltage. Different systems create different requirements for each receiver. High speed digital communication require high throughput with enough sensitivity to keep the bit error rate low. Instrumentation receivers have a lower bandwidth, but higher gain and sensitivity requirements. In this thesis an optical receiver for use in instrumentation in presented. It is an entirely monolithic design with the photodiodes on the same substrate as the CMOS circuitry. This allows for it to be built into a focal-plane array, but it places some restriction on the area. It is also designed for in-situ testing and must be able to cancel any low frequency noise caused by ambient light. The area restrictions prohibit the use of a DC blocking capacitor to reject the low frequency noise. In place a servo loop was wrapped around the system to reject any DC offset. A modified Cherry-Hooper architecture was used for the transimpedance amplifier. This provides the flexibility to create an amplifier with high gain and wide bandwidth that is independent of the input capacitance. The downside is the increased complexity of the design makes stability paramount to the design. Another drawback is the high noise associated with low input impedance that decouples the input capacitance from the bandwidth. This problem is compounded by the servo loop feed which leaves the output noise of some amplifiers directly referred to the input. An in depth analysis of each circuit block's noise contribution is presented.

Contributors

Agent

Created

Date Created
  • 2011