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Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC

As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
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Description
This dissertation presents my work on development of deformable electronics using microelectromechanical systems (MEMS) based fabrication technologies. In recent years, deformable electronics are coming to revolutionize the functionality of microelectronics seamlessly with their application environment, ranging from various consumer electronics to bio-medical applications. Many researchers have studied this area, and

This dissertation presents my work on development of deformable electronics using microelectromechanical systems (MEMS) based fabrication technologies. In recent years, deformable electronics are coming to revolutionize the functionality of microelectronics seamlessly with their application environment, ranging from various consumer electronics to bio-medical applications. Many researchers have studied this area, and a wide variety of devices have been fabricated. One traditional way is to directly fabricate electronic devices on flexible substrate through low-temperature processes. These devices suffered from constrained functionality due to the temperature limit. Another transfer printing approach has been developed recently. The general idea is to fabricate functional devices on hard and planar substrates using standard processes then transferred by elastomeric stamps and printed on desired flexible and stretchable substrates. The main disadvantages are that the transfer printing step may limit the yield. The third method is "flexible skins" which silicon substrates are thinned down and structured into islands and sandwiched by two layers of polymer. The main advantage of this method is post CMOS compatible. Based on this technology, we successfully fabricated a 3-D flexible thermal sensor for intravascular flow monitoring. The final product of the 3-D sensor has three independent sensing elements equally distributed around the wall of catheter (1.2 mm in diameter) with 120° spacing. This structure introduces three independent information channels, and cross-comparisons among all readings were utilized to eliminate experimental error and provide better measurement results. The novel fabrication and assembly technology can also be applied to other catheter based biomedical devices. A step forward inspired by the ancient art of folding, origami, which creating three-dimensional (3-D) structures from two-dimensional (2-D) sheets through a high degree of folding along the creases. Based on this idea, we developed a novel method to enable better deformability. One example is origami-enabled silicon solar cells. The solar panel can reach up to 644% areal compactness while maintain reasonable good performance (less than 30% output power density drop) upon 40 times cyclic folding/unfolding. This approach can be readily applied to other functional devices, ranging from sensors, displays, antenna, to energy storage devices.
ContributorsTang, Rui (Author) / Yu, Hongyu (Thesis advisor) / Jiang, Hanqing (Committee member) / Pan, George (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Heterogeneous multiprocessor systems-on-chip (MPSoCs) powering mobile platforms integrate multiple asymmetric CPU cores, a GPU, and many specialized processors. When the MPSoC operates close to its peak performance, power dissipation easily increases the temperature, hence adversely impacts reliability. Since using a fan is not a viable solution for hand-held devices, there

Heterogeneous multiprocessor systems-on-chip (MPSoCs) powering mobile platforms integrate multiple asymmetric CPU cores, a GPU, and many specialized processors. When the MPSoC operates close to its peak performance, power dissipation easily increases the temperature, hence adversely impacts reliability. Since using a fan is not a viable solution for hand-held devices, there is a strong need for dynamic thermal and power management (DTPM) algorithms that can regulate temperature with minimal performance impact. This abstract presents a DTPM algorithm based on a practical temperature prediction methodology using system identification. The DTPM algorithm dynamically computes a power budget using the predicted temperature, and controls the types and number of active processors as well as their frequencies. Experiments on an octa-core big.LITTLE processor and common Android apps demonstrate that the proposed technique predicts temperature within 3% accuracy, while the DTPM algorithm provides around 6x reduction in temperature variance, and as large as 16% reduction in total platform power compared to using a fan.
ContributorsSingla, Gaurav (Author) / Ogras, Umit Y. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Unver, Ali (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Feature representations for raw data is one of the most important component in a machine learning system. Traditionally, features are \textit{hand crafted} by domain experts which can often be a time consuming process. Furthermore, they do not generalize well to unseen data and novel tasks. Recently, there have been many

Feature representations for raw data is one of the most important component in a machine learning system. Traditionally, features are \textit{hand crafted} by domain experts which can often be a time consuming process. Furthermore, they do not generalize well to unseen data and novel tasks. Recently, there have been many efforts to generate data-driven representations using clustering and sparse models. This dissertation focuses on building data-driven unsupervised models for analyzing raw data and developing efficient feature representations.

Simultaneous segmentation and feature extraction approaches for silicon-pores sensor data are considered. Aggregating data into a matrix and performing low rank and sparse matrix decompositions with additional smoothness constraints are proposed to solve this problem. Comparison of several variants of the approaches and results for signal de-noising and translocation/trapping event extraction are presented. Algorithms to improve transform-domain features for ion-channel time-series signals based on matrix completion are presented. The improved features achieve better performance in classification tasks and in reducing the false alarm rates when applied to analyte detection.

Developing representations for multimedia is an important and challenging problem with applications ranging from scene recognition, multi-media retrieval and personal life-logging systems to field robot navigation. In this dissertation, we present a new framework for feature extraction for challenging natural environment sounds. Proposed features outperform traditional spectral features on challenging environmental sound datasets. Several algorithms are proposed that perform supervised tasks such as recognition and tag annotation. Ensemble methods are proposed to improve the tag annotation process.

To facilitate the use of large datasets, fast implementations are developed for sparse coding, the key component in our algorithms. Several strategies to speed-up Orthogonal Matching Pursuit algorithm using CUDA kernel on a GPU are proposed. Implementations are also developed for a large scale image retrieval system. Image-based "exact search" and "visually similar search" using the image patch sparse codes are performed. Results demonstrate large speed-up over CPU implementations and good retrieval performance is also achieved.
ContributorsSattigeri, Prasanna S (Author) / Spanias, Andreas (Thesis advisor) / Thornton, Trevor (Committee member) / Goryll, Michael (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of

Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.

The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Hydrogen sulfide (H2S) has been identified as a potential ingredient for grain boundary passivation of multicrystalline silicon. Sulfur is already established as a good surface passivation material for crystalline silicon (c-Si). Sulfur can be used both from solution and hydrogen sulfide gas. For multicrystalline silicon (mc-Si) solar cells, increasing efficiency

Hydrogen sulfide (H2S) has been identified as a potential ingredient for grain boundary passivation of multicrystalline silicon. Sulfur is already established as a good surface passivation material for crystalline silicon (c-Si). Sulfur can be used both from solution and hydrogen sulfide gas. For multicrystalline silicon (mc-Si) solar cells, increasing efficiency is a major challenge because passivation of mc-Si wafers is more difficult due to its randomly orientated crystal grains and the principal source of recombination is contributed by the defects in the bulk of the wafer and surface.

In this work, a new technique for grain boundary passivation for multicrystalline silicon using hydrogen sulfide has been developed which is accompanied by a compatible Aluminum oxide (Al2O3) surface passivation. Minority carrier lifetime measurement of the passivated samples has been performed and the analysis shows that success has been achieved in terms of passivation and compared to already existing hydrogen passivation, hydrogen sulfide passivation is actually better. Also the surface passivation by Al2O3 helps to increase the lifetime even more after post-annealing and this helps to attain stability for the bulk passivated samples. Minority carrier lifetime is directly related to the internal quantum efficiency of solar cells. Incorporation of this technique in making mc-Si solar cells is supposed to result in higher efficiency cells. Additional research is required in this field for the use of this technique in commercial solar cells.
ContributorsSaha, Arunodoy, Ph.D (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Biogenic silica nanostructures, derived from diatoms, possess highly ordered porous hierarchical nanostructures and afford flexibility in design in large part due to the availability of a great variety of shapes, sizes, and symmetries. These advantages have been exploited for study of transport phenomena of ions and molecules towards the goal

Biogenic silica nanostructures, derived from diatoms, possess highly ordered porous hierarchical nanostructures and afford flexibility in design in large part due to the availability of a great variety of shapes, sizes, and symmetries. These advantages have been exploited for study of transport phenomena of ions and molecules towards the goal of developing ultrasensitive and selective filters and biosensors. Diatom frustules give researchers many inspiration and ideas for the design and production of novel nanostructured materials. In this doctoral research will focus on the following three aspects of biogenic silica: 1) Using diatom frustule as protein sensor. 2) Using diatom nanostructures as template to fabricate nano metal materials. 3) Using diatom nanostructures to fabricate hybrid platform.

Nanoscale confinement biogenetic silica template-based electrical biosensor assay offers the user the ability to detect and quantify the biomolecules. Diatoms have been demonstrated as part of a sensor. The sensor works on the principle of electrochemical impedance spectroscopy. When specific protein biomarkers from a test sample bind to corresponding antibodies conjugated to the surface of the gold surface at the base of each nanowell, a perturbation of electrical double layer occurs resulting in a change in the impedance.

Diatoms are also a new source of inspiration for the design and fabrication of nanostructured materials. Template-directed deposition within cylindrical nanopores of a porous membrane represents an attractive and reproducible approach for preparing metal nanopatterns or nanorods of a variety of aspect ratios. The nanopatterns fabricated from diatom have the potential of the metal-enhanced fluorescence to detect dye-conjugated molecules.

Another approach presents a platform integrating biogenic silica nanostructures with micromachined silicon substrates in a micro
ano hybrid device. In this study, one can take advantages of the unique properties of a marine diatom that exhibits nanopores on the order of 40 nm in diameter and a hierarchical structure. This device can be used to several applications, such as nano particles separation and detection. This platform is also a good substrate to study cell growth that one can observe the reaction of cell growing on the nanostructure of frustule.
ContributorsLin, Kai-Chun (Author) / Ramakrishna, B.L. (Thesis advisor) / Goryll, Michael (Thesis advisor) / Dey, Sandwip (Committee member) / Prasad, Shalini (Committee member) / Arizona State University (Publisher)
Created2014
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Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for

Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
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Description
In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase

In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral analysis of output from the BiST circuitry using an analytical method. Matlab was used to simulate the system with known test impairments and impairment values from simulations were calculated based on system modeling in Mathematica. Simulated data is in good correlation with input test data along with very fast test time and high accuracy. The key contribution of the work is that, system impairments are extracted from transmitter response at baseband frequency using envelope detector hence eliminating the need of expensive high frequency ATE (Automated Test Equipments).
ContributorsGoyal, Nitin (Author) / Ozev, Sule (Thesis advisor) / Duman, Tolga (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented

Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011