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Description
Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power,

Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power, better performance and lower hardware cost.

First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 and 3), x8 (Scheme 4) and x16 (Scheme 5) DRAM systems. All schemes have superior error correction performance due to the use of strong symbol-based codes. In addition, the use of erasure codes extends the lifetime of the 2D DRAM systems.

Next, two error correction schemes are presented for 3D DRAM memory systems. The first scheme is a rate-adaptive, two-tiered error correction scheme (RATT-ECC) that provides strong reliability (10^10x) reduction in raw FIT rate) for an HBM-like 3D DRAM system that services CPU applications. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing the reliability and timing performance.

The second scheme is a two-tiered error correction scheme (Config-ECC) that supports different sized accesses in GPU applications with strong reliability. It addresses the mismatch between data access size and fixed sized ECC scheme by designing a product code based flexible scheme. Config-ECC is built around a core unit designed for 32B access with a simple extension to support 64B and 128B accesses. Compared to fixed 32B and 64B ECC schemes, Config-ECC reduces the failure in time (FIT) rate by 200x and 20x, respectively. It also reduces the memory energy by 17% (in the dynamic mode) and 21% (in the static mode) compared to a state-of-the-art fixed 64B ECC scheme.
ContributorsChen, Hsing-Min (Author) / Chakrabarti, Chaitali (Thesis advisor) / Mudge, Trevor (Committee member) / Wu, Carole-Jean (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2017
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Created1925-19-39 (uncertain)
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Created1934
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Created1926
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Created1926
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Created1926
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Created1928
Description

Human Papillomavirus, or HPV, is a viral pathogen that most commonly spreads through sexual contact. HPV strains 6 and 11 normally cause genital warts, while HPV strains 16 and 18 commonly cause cervical cancer, which causes cancerous cells to spread in the cervix. Physicians can detect those HPV strains, using

Human Papillomavirus, or HPV, is a viral pathogen that most commonly spreads through sexual contact. HPV strains 6 and 11 normally cause genital warts, while HPV strains 16 and 18 commonly cause cervical cancer, which causes cancerous cells to spread in the cervix. Physicians can detect those HPV strains, using a Pap smear, which is a diagnostic test that collects cells from the female cervix.

Created2021-04-06
Description

Johann Gregor Mendel studied patterns of trait inheritance in plants during the nineteenth century. Mendel, an Augustinian monk, conducted experiments on pea plants at St. Thomas’ Abbey in what is now Brno, Czech Republic. Twentieth century scientists used Mendel’s recorded observations to create theories about genetics.

Created2022-01-13