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- Member of: ASU Electronic Theses and Dissertations
Description
Recently, the use of zinc oxide (ZnO) nanowires as an interphase in composite materials has been demonstrated to increase the interfacial shear strength between carbon fiber and an epoxy matrix. In this research work, the strong adhesion between ZnO and carbon fiber is investigated to elucidate the interactions at the interface that result in high interfacial strength. First, molecular dynamics (MD) simulations are performed to calculate the adhesive energy between bare carbon and ZnO. Since the carbon fiber surface has oxygen functional groups, these were modeled and MD simulations showed the preference of ketones to strongly interact with ZnO, however, this was not observed in the case of hydroxyls and carboxylic acid. It was also found that the ketone molecules ability to change orientation facilitated the interactions with the ZnO surface. Experimentally, the atomic force microscope (AFM) was used to measure the adhesive energy between ZnO and carbon through a liftoff test by employing highly oriented pyrolytic graphite (HOPG) substrate and a ZnO covered AFM tip. Oxygen functionalization of the HOPG surface shows the increase of adhesive energy. Additionally, the surface of ZnO was modified to hold a negative charge, which demonstrated an increase in the adhesive energy. This increase in adhesion resulted from increased induction forces given the relatively high polarizability of HOPG and the preservation of the charge on ZnO surface. It was found that the additional negative charge can be preserved on the ZnO surface because there is an energy barrier since carbon and ZnO form a Schottky contact. Other materials with the same ionic properties of ZnO but with higher polarizability also demonstrated good adhesion to carbon. This result substantiates that their induced interaction can be facilitated not only by the polarizability of carbon but by any of the materials at the interface. The versatility to modify the magnitude of the induced interaction between carbon and an ionic material provides a new route to create interfaces with controlled interfacial strength.
ContributorsGalan Vera, Magdian Ulises (Author) / Sodano, Henry A (Thesis advisor) / Jiang, Hanqing (Committee member) / Solanki, Kiran (Committee member) / Oswald, Jay (Committee member) / Speyer, Gil (Committee member) / Arizona State University (Publisher)
Created2013
Description
"Sensor Decade" has been labeled on the first decade of the 21st century. Similar to the revolution of micro-computer in 1980s, sensor R&D; developed rapidly during the past 20 years. Hard workings were mainly made to minimize the size of devices with optimal the performance. Efforts to develop the small size devices are mainly concentrated around Micro-electro-mechanical-system (MEMS) technology. MEMS accelerometers are widely published and used in consumer electronics, such as smart phones, gaming consoles, anti-shake camera and vibration detectors. This study represents liquid-state low frequency micro-accelerometer based on molecular electronic transducer (MET), in which inertial mass is not the only but also the conversion of mechanical movement to electric current signal is the main utilization of the ionic liquid. With silicon-based planar micro-fabrication, the device uses a sub-micron liter electrolyte droplet sealed in oil as the sensing body and a MET electrode arrangement which is the anode-cathode-cathode-anode (ACCA) in parallel as the read-out sensing part. In order to sensing the movement of ionic liquid, an imposed electric potential was applied between the anode and the cathode. The electrode reaction, I_3^-+2e^___3I^-, occurs around the cathode which is reverse at the anodes. Obviously, the current magnitude varies with the concentration of ionic liquid, which will be effected by the movement of liquid droplet as the inertial mass. With such structure, the promising performance of the MET device design is to achieve 10.8 V/G (G=9.81 m/s^2) sensitivity at 20 Hz with the bandwidth from 1 Hz to 50 Hz, and a low noise floor of 100 ug/sqrt(Hz) at 20 Hz.
ContributorsLiang, Mengbing (Author) / Yu, Hongyu (Thesis advisor) / Jiang, Hanqing (Committee member) / Kozicki, Micheal (Committee member) / Arizona State University (Publisher)
Created2013
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description
Woven fabric composite materials are widely used in the construction of aircraft engine fan containment systems, mostly due to their high strength to weight ratios and ease of implementation. The development of a predictive model for fan blade containment would provide great benefit to engine manufactures in shortened development cycle time, less risk in certification and fewer dollars lost to redesign/recertification cycles. A mechanistic user-defined material model subroutine has been developed at Arizona State University (ASU) that captures the behavioral response of these fabrics, namely Kevlar® 49, under ballistic loading. Previously developed finite element models used to validate the consistency of this material model neglected the effects of the physical constraints imposed on the test setup during ballistic testing performed at NASA Glenn Research Center (NASA GRC). Part of this research was to explore the effects of these boundary conditions on the results of the numerical simulations. These effects were found to be negligible in most instances. Other material models for woven fabrics are available in the LS-DYNA finite element code. One of these models, MAT234: MAT_VISCOELASTIC_LOOSE_FABRIC (Ivanov & Tabiei, 2004) was studied and implemented in the finite element simulations of ballistic testing associated with the FAA ASU research. The results from these models are compared to results obtained from the ASU UMAT as part of this research. The results indicate an underestimation in the energy absorption characteristics of the Kevlar 49 fabric containment systems. More investigation needs to be performed in the implementation of MAT234 for Kevlar 49 fabric. Static penetrator testing of Kevlar® 49 fabric was performed at ASU in conjunction with this research. These experiments are designed to mimic the type of loading experienced during fan blade out events. The resulting experimental strains were measured using a non-contact optical strain measurement system (ARAMIS).
ContributorsFein, Jonathan (Author) / Rajan, Subramaniam D. (Thesis advisor) / Mobasher, Barzin (Committee member) / Jiang, Hanqing (Committee member) / Arizona State University (Publisher)
Created2012
Description
Dealloying induced stress corrosion cracking is particularly relevant in energy conversion systems (both nuclear and fossil fuel) as many failures in alloys such as austenitic stainless steel and nickel-based systems result directly from dealloying. This study provides evidence of the role of unstable dynamic fracture processes in dealloying induced stress-corrosion cracking of face-centered cubic alloys. Corrosion of such alloys often results in the formation of a brittle nanoporous layer which we hypothesize serves to nucleate a crack that owing to dynamic effects penetrates into the un-dealloyed parent phase alloy. Thus, since there is essentially a purely mechanical component of cracking, stress corrosion crack propagation rates can be significantly larger than that predicted from electrochemical parameters. The main objective of this work is to examine and test this hypothesis under conditions relevant to stress corrosion cracking. Silver-gold alloys serve as a model system for this study since hydrogen effects can be neglected on a thermodynamic basis, which allows us to focus on a single cracking mechanism. In order to study various aspects of this problem, the dynamic fracture properties of monolithic nanoporous gold (NPG) were examined in air and under electrochemical conditions relevant to stress corrosion cracking. The detailed processes associated with the crack injection phenomenon were also examined by forming dealloyed nanoporous layers of prescribed properties on un-dealloyed parent phase structures and measuring crack penetration distances. Dynamic fracture in monolithic NPG and in crack injection experiments was examined using high-speed (106 frames s-1) digital photography. The tunable set of experimental parameters included the NPG length scale (20-40 nm), thickness of the dealloyed layer (10-3000 nm) and the electrochemical potential (0.5-1.5 V). The results of crack injection experiments were characterized using the dual-beam focused ion beam/scanning electron microscopy. Together these tools allow us to very accurately examine the detailed structure and composition of dealloyed grain boundaries and compare crack injection distances to the depth of dealloying. The results of this work should provide a basis for new mathematical modeling of dealloying induced stress corrosion cracking while providing a sound physical basis for the design of new alloys that may not be susceptible to this form of cracking. Additionally, the obtained results should be of broad interest to researchers interested in the fracture properties of nano-structured materials. The findings will open up new avenues of research apart from any implications the study may have for stress corrosion cracking.
ContributorsSun, Shaofeng (Author) / Sieradzki, Karl (Thesis advisor) / Jiang, Hanqing (Committee member) / Peralta, Pedro (Committee member) / Arizona State University (Publisher)
Created2012
Description
The focus of this investigation is on the optimum placement of a limited number of dampers, fewer than the number of blades, on a bladed disk to induce the smallest amplitude of blade response. The optimization process considers the presence of random mistuning, i.e. small involuntary variations in blade stiffness properties resulting, say, from manufacturing variability. Designed variations of these properties, known as intentional mistuning, is considered as an option to reduce blade response and the pattern of two blade types (A and B blades) is then part of the optimization in addition to the location of dampers on the disk. First, this study focuses on the formulation and validation of dedicated algorithms for the selection of the damper locations and the intentional mistuning pattern. Failure of one or several of the dampers could lead to a sharp rise in blade response and this issue is addressed by including, in the optimization, the possibility of damper failure to yield a fail-safe solution. The high efficiency and accuracy of the optimization algorithms is assessed in comparison with computationally very demanding exhaustive search results. Second, the developed optimization algorithms are applied to nonlinear dampers (underplatform friction dampers), as well as to blade-blade dampers, both linear and nonlinear. Further, the optimization of blade-only and blade-blade linear dampers is extended to include uncertainty or variability in the damper properties induced by manufacturing or wear. It is found that the optimum achieved without considering such uncertainty is robust with respect to it. Finally, the potential benefits of using two different types of friction dampers differing in their masses (A and B types), on a bladed disk are considered. Both A/B pattern and the damper masses are optimized to obtain the largest benefit compared to using identical dampers of optimized masses on every blade. Four situations are considered: tuned disks, disks with random mistuning of blade stiffness, and, disks with random mistuning of both blade stiffness and damper normal forces with and without damper variability induced by manufacturing and wear. In all cases, the benefit of intentional mistuning of friction dampers is small, of the order of a few percent.
ContributorsMurthy, Raghavendra Narasimha (Author) / Mignolet, Marc P (Thesis advisor) / Rajan, Subramaniam D. (Committee member) / Lentz, Jeff (Committee member) / Chattopadhyay, Aditi (Committee member) / Jiang, Hanqing (Committee member) / Arizona State University (Publisher)
Created2012
Description
Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.
ContributorsFallah-Adl, Ali (Author) / Tasooji, Amaneh (Thesis advisor) / Krause, Stephen (Committee member) / Alford, Terry (Committee member) / Jiang, Hanqing (Committee member) / Mahajan, Ravi (Committee member) / Arizona State University (Publisher)
Created2013
Description
Shock loading is a complex phenomenon that can lead to failure mechanisms such as strain localization, void nucleation and growth, and eventually spall fracture. Studying incipient stages of spall damage is of paramount importance to accurately determine initiation sites in the material microstructure where damage will nucleate and grow and to formulate continuum models that account for the variability of the damage process due to microstructural heterogeneity. The length scale of damage with respect to that of the surrounding microstructure has proven to be a key aspect in determining sites of failure initiation. Correlations have been found between the damage sites and the surrounding microstructure to determine the preferred sites of spall damage, since it tends to localize at and around the regions of intrinsic defects such as grain boundaries and triple points. However, considerable amount of work still has to be done in this regard to determine the physics driving the damage at these intrinsic weak sites in the microstructure. The main focus of this research work is to understand the physical mechanisms behind the damage localization at these preferred sites. A crystal plasticity constitutive model is implemented with different damage criteria to study the effects of stress concentration and strain localization at the grain boundaries. A cohesive zone modeling technique is used to include the intrinsic strength of the grain boundaries in the simulations. The constitutive model is verified using single elements tests, calibrated using single crystal impact experiments and validated using bicrystal and multicrystal impact experiments. The results indicate that strain localization is the predominant driving force for damage initiation and evolution. The microstructural effects on theses damage sites are studied to attribute the extent of damage to microstructural features such as grain orientation, misorientation, Taylor factor and the grain boundary planes. The finite element simulations show good correlation with the experimental results and can be used as the preliminary step in developing accurate probabilistic models for damage nucleation.
ContributorsKrishnan, Kapil (Author) / Peralta, Pedro (Thesis advisor) / Mignolet, Marc (Committee member) / Sieradzki, Karl (Committee member) / Jiang, Hanqing (Committee member) / Oswald, Jay (Committee member) / Arizona State University (Publisher)
Created2013
Description
Rapid technology scaling, the main driver of the power and performance improvements of computing solutions, has also rendered our computing systems extremely susceptible to transient errors called soft errors. Among the arsenal of techniques to protect computation from soft errors, Control Flow Checking (CFC) based techniques have gained a reputation of effective, yet low-cost protection mechanism. The basic idea is that, there is a high probability that a soft-fault in program execution will eventually alter the control flow of the program. Therefore just by making sure that the control flow of the program is correct, significant protection can be achieved. More than a dozen techniques for CFC have been developed over the last several decades, ranging from hardware techniques, software techniques, and hardware-software hybrid techniques as well. Our analysis shows that existing CFC techniques are not only ineffective in protecting from soft errors, but cause additional power and performance overheads. For this analysis, we develop and validate a simulation based experimental setup to accurately and quantitatively estimate the architectural vulnerability of a program execution on a processor micro-architecture. We model the protection achieved by various state-of-the-art CFC techniques in this quantitative vulnerability estimation setup, and find out that software only CFC protection schemes (CFCSS, CFCSS+NA, CEDA) increase system vulnerability by 18% to 21% with 17% to 38% performance overhead. Hybrid CFC protection (CFEDC) increases vulnerability by 5%, while the vulnerability remains almost the same for hardware only CFC protection (CFCET); notwithstanding the hardware overheads of design cost, area, and power incurred in the hardware modifications required for their implementations.
ContributorsRhisheekesan, Abhishek (Author) / Shrivastava, Aviral (Thesis advisor) / Colbourn, Charles Joseph (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Created2013
Description
We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures. Software Managed Manycore (SMM) architectures emerge as a solution. They have scalable memory design in which each core has direct access to only its local scratchpad memory, and any data transfers to/from other memories must be done explicitly in the application using Direct Memory Access (DMA) commands. Lack of automatic memory management in the hardware makes such architectures extremely power-efficient, but they also become difficult to program. If the code/data of the task mapped onto a core cannot fit in the local scratchpad memory, then DMA calls must be added to bring in the code/data before it is required, and it may need to be evicted after its use. However, doing this adds a lot of complexity to the programmer's job. Now programmers must worry about data management, on top of worrying about the functional correctness of the program - which is already quite complex. This dissertation presents a comprehensive compiler and runtime integration to automatically manage the code and data of each task in the limited local memory of the core. We firstly developed a Complete Circular Stack Management. It manages stack frames between the local memory and the main memory, and addresses the stack pointer problem as well. Though it works, we found we could further optimize the management for most cases. Thus a Smart Stack Data Management (SSDM) is provided. In this work, we formulate the stack data management problem and propose a greedy algorithm for the same. Later on, we propose a general cost estimation algorithm, based on which CMSM heuristic for code mapping problem is developed. Finally, heap data is dynamic in nature and therefore it is hard to manage it. We provide two schemes to manage unlimited amount of heap data in constant sized region in the local memory. In addition to those separate schemes for different kinds of data, we also provide a memory partition methodology.
ContributorsBai, Ke (Author) / Shrivastava, Aviral (Thesis advisor) / Chatha, Karamvir (Committee member) / Xue, Guoliang (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2014