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- Genre: Academic theses
- Creators: Bakkaloglu, Bertan
- Creators: Vittal, Vijay
- Status: Published
Description
Switching Converters (SC) are an excellent choice for hand held devices due to their high power conversion efficiency. However, they suffer from two major drawbacks. The first drawback is that their dynamic response is sensitive to variations in inductor (L) and capacitor (C) values. A cost effective solution is implemented by designing a programmable digital controller. Despite variations in L and C values, the target dynamic response can be achieved by computing and programming the filter coefficients for a particular L and C. Besides, digital controllers have higher immunity to environmental changes such as temperature and aging of components. The second drawback of SCs is their poor efficiency during low load conditions if operated in Pulse Width Modulation (PWM) mode. However, if operated in Pulse Frequency Modulation (PFM) mode, better efficiency numbers can be achieved. A mostly-digital way of detecting PFM mode is implemented. Besides, a slow serial interface to program the chip, and a high speed serial interface to characterize mixed signal blocks as well as to ship data in or out for debug purposes are designed. The chip is taped out in 0.18µm IBM's radiation hardened CMOS process technology. A test board is built with the chip, external power FETs and driver IC. At the time of this writing, PWM operation, PFM detection, transitions between PWM and PFM, and both serial interfaces are validated on the test board.
ContributorsMumma Reddy, Abhiram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
There has been a considerable growth in distributed photovoltaic (PV) genera-tion and its integration in electric power distribution systems. This has led to a change in the distribution system infrastructure. Properly planned distributed gen-eration can offer a variety of benefits for system operations and enhance opera-tional performance of the distribution system. However, high penetration of PV resources can give rise to operating conditions which do not arise in traditional systems and one of the potential issues that needs to be addressed involves impact on power quality of the system with respect to the spectral distortion in voltages and currents.
The test bed feeder model representing a real operational distribution feeder is developed in OpenDSS and the feeder modeling takes into consideration the ob-jective of analysis and frequency of interest. Extensive metering infrastructure and measurements are utilized for validation of the model at harmonic frequencies. The harmonic study performed is divided into two sections: study of impact of non-linear loads on total harmonic voltage and current distortions and study of impact of PV resources on high frequency spectral distortion in voltages and cur-rents. The research work incorporates different harmonic study methodologies such as harmonic and high frequency power flow, and frequency scan study. The general conclusions are presented based on the simulation results and in addition, scope for future work is discussed.
The test bed feeder model representing a real operational distribution feeder is developed in OpenDSS and the feeder modeling takes into consideration the ob-jective of analysis and frequency of interest. Extensive metering infrastructure and measurements are utilized for validation of the model at harmonic frequencies. The harmonic study performed is divided into two sections: study of impact of non-linear loads on total harmonic voltage and current distortions and study of impact of PV resources on high frequency spectral distortion in voltages and cur-rents. The research work incorporates different harmonic study methodologies such as harmonic and high frequency power flow, and frequency scan study. The general conclusions are presented based on the simulation results and in addition, scope for future work is discussed.
ContributorsJoshi, Titiksha Vjay (Author) / Heydt, Gerald T (Thesis advisor) / Ayyanar, Raja (Committee member) / Vittal, Vijay (Committee member) / Arizona State University (Publisher)
Created2014
Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
Heterogeneous multiprocessor systems-on-chip (MPSoCs) powering mobile platforms integrate multiple asymmetric CPU cores, a GPU, and many specialized processors. When the MPSoC operates close to its peak performance, power dissipation easily increases the temperature, hence adversely impacts reliability. Since using a fan is not a viable solution for hand-held devices, there is a strong need for dynamic thermal and power management (DTPM) algorithms that can regulate temperature with minimal performance impact. This abstract presents a DTPM algorithm based on a practical temperature prediction methodology using system identification. The DTPM algorithm dynamically computes a power budget using the predicted temperature, and controls the types and number of active processors as well as their frequencies. Experiments on an octa-core big.LITTLE processor and common Android apps demonstrate that the proposed technique predicts temperature within 3% accuracy, while the DTPM algorithm provides around 6x reduction in temperature variance, and as large as 16% reduction in total platform power compared to using a fan.
ContributorsSingla, Gaurav (Author) / Ogras, Umit Y. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Unver, Ali (Committee member) / Arizona State University (Publisher)
Created2015
Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
ContributorsPadala, Sudheer (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
This thesis presents research on innovative AC transmission design concepts and focused mathematics for electric power transmission design. The focus relates to compact designs, high temperature low sag conductors, and high phase order design. The motivation of the research is to increase transmission capacity with limited right of way.
Regarding compact phase spacing, insight into the possibility of increasing the security rating of transmission lines is the primary focus through increased mutual coupling and decreased positive sequence reactance. Compact design can reduce the required corridor width to as little as 31% of traditional designs, especially with the use of inter-phase spacers. Typically transmission lines are built with conservative clearances, with difficulty obtaining right of way, more compact phase spacing may be needed. With design consideration significant compaction can produce an increase by 5-25% in the transmission line security (steady state stability) rating. In addition, other advantages and disadvantages of compact phase design are analyzed. Also, the next two topics: high temperature low sag conductors and high phase order designs include the use of compact designs.
High temperature low sag (HTLS) conductors are used to increase the thermal capacity of a transmission line up to two times the capacity compared to traditional conductors. HTLS conductors can operate continuously at 150-210oC and in emergency at 180-250oC (depending on the HTLS conductor). ACSR conductors operate continuously at 50-110oC and in emergency conditions at 110-150oC depending on the utility, line, and location. HTLS conductors have decreased sag characteristics of up to 33% compared to traditional ACSR conductors at 100oC and up to 22% at 180oC. In addition to what HTLS has to offer in terms of the thermal rating improvement, the possibility of using HTLS conductors to indirectly reduce tower height and compact the phases to increase the security limit is investigated. In addition, utilizing HTLS conductors to increase span length and decrease the number of transmission towers is investigated. The phase compaction or increased span length is accomplished by utilization of the improved physical sag characteristics of HTLS conductors.
High phase order (HPO) focuses on the ability to increase the power capacity for a given right of way. For example, a six phase line would have a thermal rating of approximately 173%, a security rating of approximately 289%, and the SIL would be approximately 300% of a double circuit three phase line with equal right of way and equal voltage line to line. In addition, this research focuses on algorithm and model development of HPO systems. A study of the impedance of HPO lines is presented. The line impedance matrices for some high phase order configurations are circulant Toeplitz matrices. Properties of circulant matrices are developed for the generalized sequence impedances of HPO lines. A method to calculate the sequence impedances utilizing unique distance parameter algorithms is presented. A novel method to design the sequence impedances to specifications is presented. Utilizing impedance matrices in circulant form, a generalized form of the sequence components transformation matrix is presented. A generalized voltage unbalance factor in discussed for HPO transmission lines. Algorithms to calculate the number of fault types and number of significant fault types for an n-phase system are presented. A discussion is presented on transposition of HPO transmission lines and a generalized fault analysis of a high phase order circuit is presented along with an HPO analysis program.
The work presented has the objective of increasing the use of rights of way for bulk power transmission through the use of innovative transmission technologies. The purpose of this dissertation is to lay down some of the building blocks and to help make the three technologies discussed practical applications in the future.
Regarding compact phase spacing, insight into the possibility of increasing the security rating of transmission lines is the primary focus through increased mutual coupling and decreased positive sequence reactance. Compact design can reduce the required corridor width to as little as 31% of traditional designs, especially with the use of inter-phase spacers. Typically transmission lines are built with conservative clearances, with difficulty obtaining right of way, more compact phase spacing may be needed. With design consideration significant compaction can produce an increase by 5-25% in the transmission line security (steady state stability) rating. In addition, other advantages and disadvantages of compact phase design are analyzed. Also, the next two topics: high temperature low sag conductors and high phase order designs include the use of compact designs.
High temperature low sag (HTLS) conductors are used to increase the thermal capacity of a transmission line up to two times the capacity compared to traditional conductors. HTLS conductors can operate continuously at 150-210oC and in emergency at 180-250oC (depending on the HTLS conductor). ACSR conductors operate continuously at 50-110oC and in emergency conditions at 110-150oC depending on the utility, line, and location. HTLS conductors have decreased sag characteristics of up to 33% compared to traditional ACSR conductors at 100oC and up to 22% at 180oC. In addition to what HTLS has to offer in terms of the thermal rating improvement, the possibility of using HTLS conductors to indirectly reduce tower height and compact the phases to increase the security limit is investigated. In addition, utilizing HTLS conductors to increase span length and decrease the number of transmission towers is investigated. The phase compaction or increased span length is accomplished by utilization of the improved physical sag characteristics of HTLS conductors.
High phase order (HPO) focuses on the ability to increase the power capacity for a given right of way. For example, a six phase line would have a thermal rating of approximately 173%, a security rating of approximately 289%, and the SIL would be approximately 300% of a double circuit three phase line with equal right of way and equal voltage line to line. In addition, this research focuses on algorithm and model development of HPO systems. A study of the impedance of HPO lines is presented. The line impedance matrices for some high phase order configurations are circulant Toeplitz matrices. Properties of circulant matrices are developed for the generalized sequence impedances of HPO lines. A method to calculate the sequence impedances utilizing unique distance parameter algorithms is presented. A novel method to design the sequence impedances to specifications is presented. Utilizing impedance matrices in circulant form, a generalized form of the sequence components transformation matrix is presented. A generalized voltage unbalance factor in discussed for HPO transmission lines. Algorithms to calculate the number of fault types and number of significant fault types for an n-phase system are presented. A discussion is presented on transposition of HPO transmission lines and a generalized fault analysis of a high phase order circuit is presented along with an HPO analysis program.
The work presented has the objective of increasing the use of rights of way for bulk power transmission through the use of innovative transmission technologies. The purpose of this dissertation is to lay down some of the building blocks and to help make the three technologies discussed practical applications in the future.
ContributorsPierre, Brian J (Author) / Heydt, Gerald (Thesis advisor) / Karady, George G. (Committee member) / Shunk, Dan (Committee member) / Vittal, Vijay (Committee member) / Arizona State University (Publisher)
Created2015
Description
Due to restructuring and open access to the transmission system, modern electric power systems are being operated closer to their operational limits. Additionally, the secure operational limits of modern power systems have become increasingly difficult to evaluate as the scale of the network and the number of transactions between utilities increase. To account for these challenges associated with the rapid expansion of electric power systems, dynamic equivalents have been widely applied for the purpose of reducing the computational effort of simulation-based transient security assessment. Dynamic equivalents are commonly developed using a coherency-based approach in which a retained area and an external area are first demarcated. Then the coherent generators in the external area are aggregated and replaced by equivalenced models, followed by network reduction and load aggregation. In this process, an improperly defined retained area can result in detrimental impacts on the effectiveness of the equivalents in preserving the dynamic characteristics of the original unreduced system. In this dissertation, a comprehensive approach has been proposed to determine an appropriate retained area boundary by including the critical generators in the external area that are tightly coupled with the initial retained area. Further-more, a systematic approach has also been investigated to efficiently predict the variation in generator slow coherency behavior when the system operating condition is subject to change. Based on this determination, the critical generators in the external area that are tightly coherent with the generators in the initial retained area are retained, resulting in a new retained area boundary. Finally, a novel hybrid dynamic equivalent, consisting of both a coherency-based equivalent and an artificial neural network (ANN)-based equivalent, has been proposed and analyzed. The ANN-based equivalent complements the coherency-based equivalent at all the retained area boundary buses, and it is designed to compensate for the discrepancy between the full system and the conventional coherency-based equivalent. The approaches developed have been validated on a large portion of the Western Electricity Coordinating Council (WECC) system and on a test case including a significant portion of the eastern interconnection.
ContributorsMa, Feng (Author) / Vittal, Vijay (Thesis advisor) / Tylavsky, Daniel (Committee member) / Heydt, Gerald (Committee member) / Si, Jennie (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral analysis of output from the BiST circuitry using an analytical method. Matlab was used to simulate the system with known test impairments and impairment values from simulations were calculated based on system modeling in Mathematica. Simulated data is in good correlation with input test data along with very fast test time and high accuracy. The key contribution of the work is that, system impairments are extracted from transmitter response at baseband frequency using envelope detector hence eliminating the need of expensive high frequency ATE (Automated Test Equipments).
ContributorsGoyal, Nitin (Author) / Ozev, Sule (Thesis advisor) / Duman, Tolga (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011