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Aging predictive models and simulation methods for analog and mixed-signal circuits

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Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient simulation methods are essential for circuit level reliability prediction. This work proposes a set of

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient simulation methods are essential for circuit level reliability prediction. This work proposes a set of compact models of NBTI and CHC effects for analog and mixed-signal circuit, and a direct prediction method which is different from conventional simulation methods. This method is applied in circuit benchmarks and evaluated. This work helps with improving efficiency and accuracy of circuit aging prediction.

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2011

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Molecular electronic transducer-based seismometer and accelerometer fabricated with micro-electro-mechanical systems techniques

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This thesis presents approaches to develop micro seismometers and accelerometers based on molecular electronic transducers (MET) technology using MicroElectroMechanical Systems (MEMS) techniques. MET is a technology applied in seismic instrumentation that proves highly beneficial to planetary seismology. It consists of

This thesis presents approaches to develop micro seismometers and accelerometers based on molecular electronic transducers (MET) technology using MicroElectroMechanical Systems (MEMS) techniques. MET is a technology applied in seismic instrumentation that proves highly beneficial to planetary seismology. It consists of an electrochemical cell that senses the movement of liquid electrolyte between electrodes by converting it to the output current. MET seismometers have advantages of high sensitivity, low noise floor, small size, absence of fragile mechanical moving parts and independence on the direction of sensitivity axis. By using MEMS techniques, a micro MET seismometer is developed with inter-electrode spacing close to 1μm, which improves the sensitivity of fabricated device to above 3000 V/(m/s^2) under operating bias of 600 mV and input acceleration of 400 μG (G=9.81m/s^2) at 0.32 Hz. The lowered hydrodynamic resistance by increasing the number of channels improves the self-noise to -127 dB equivalent to 44 nG/√Hz at 1 Hz. An alternative approach to build the sensing element of MEMS MET seismometer using SOI process is also presented in this thesis. The significantly increased number of channels is expected to improve the noise performance. Inspired by the advantages of combining MET and MEMS technologies on the development of seismometer, a low frequency accelerometer utilizing MET technology with post-CMOS-compatible fabrication processes is developed. In the fabricated accelerometer, the complicated fabrication of mass-spring system in solid-state MEMS accelerometer is replaced with a much simpler post-CMOS-compatible process containing only deposition of a four-electrode MET structure on a planar substrate, and a liquid inertia mass of an electrolyte droplet encapsulated by oil film. The fabrication process does not involve focused ion beam milling which is used in the micro MET seismometer fabrication, thus the cost is lowered. Furthermore, the planar structure and the novel idea of using an oil film as the sealing diaphragm eliminate the complicated three-dimensional packaging of the seismometer. The fabricated device achieves 10.8 V/G sensitivity at 20 Hz with nearly flat response over the frequency range from 1 Hz to 50 Hz, and a low noise floor of 75 μG/√Hz at 20 Hz.

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2014

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A CMOS analog front-end circuit for micro-fluxgate sensors

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Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high

Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high sensitivity and low noise. The major application of fluxgate sensors is in magnetometers for the measurement of earth's magnetic field. Magnetometers are used in navigation systems and electronic compasses. Fluxgate sensors can also be used to measure high DC currents. Integrated micro-fluxgate sensors have been developed in recent years. These sensors have much lower power consumption and area compared to their PCB counterparts. The output voltage of micro-fluxgate sensors is very low which makes the analog front end more complex and results in an increase in power consumption of the system. In this thesis a new analog front-end circuit for micro-fluxgate sensors is developed. This analog front-end circuit uses charge pump based excitation circuit and phase delay based read-out chain. With these two features the power consumption of analog front-end is reduced. The output is digital and it is immune to amplitude noise at the output of the sensor. Digital output is produced without using an ADC. A SPICE model of micro-fluxgate sensor is used to verify the operation of the analog front-end and the simulation results show very good linearity.

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2013

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Design of a twelve bit, four hundred mega-samples-per-second, interpolating dual channel digital to analog converter featuring digital modulation

Description

Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and

Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and feature on chip digital mixing. Digital mixing offers many benefits concerning I and Q matching but has one major drawback; the update rate of the DAC must be higher than the intermediate frequency (IF) which is most commonly a factor of 4. This drawback motivates the need for interpolation so that a low update rate can be used for components preceding the DACs. In this thesis the design of an interpolating DAC integrated circuit (IC) to be used in a transmitter application for generating a 100MHz IF is presented. Many of the transistor level implementations are provided. The tradeoffs in the design are analyzed and various options are discussed. This thesis provides a basic foundation for designing an IC of this nature and will give the reader insight into potential areas of further research. At the time of this writing the chip is in fabrication therefore this document does not contain test results.

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2013

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Analysis, design, simulation, and measurements of flexible high impedance surfaces

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High Impedance Surfaces (HISs), which have been investigated extensively, have proven to be very efficient ground planes for low profile antenna applications due to their unique reflection phase characteristics. Another emerging research field among the microwave and antenna technologies is

High Impedance Surfaces (HISs), which have been investigated extensively, have proven to be very efficient ground planes for low profile antenna applications due to their unique reflection phase characteristics. Another emerging research field among the microwave and antenna technologies is the design of flexible antennas and microwave circuits to be utilized in conformal applications. The combination of those two research topics gives birth to a third one, namely the design of Conformal or Flexible HISs (FHISs), which is the main subject of this dissertation. The problems associated with the FHISs are twofold: characterization and physical realization. The characterization involves the analysis of scattering properties of FHISs in the presence of plane wave and localized sources. For this purpose, an approximate analytical method is developed to characterize the reflection properties of a cylindrically curved FHIS. The effects of curvature on the reflection phase of the curved FHISs are examined. Furthermore, the effects of different types of currents, specifically the ones inherent to finite sized periodic structures, on the reflection phase characteristics are observed. After the reflection phase characterization of curved HISs, the performance of dipole antennas located in close proximity to a curved HIS are investigated, and the results are compared with the flat case. Different types of resonances that may occur for such a low-profile antenna application are discussed. The effects of curvature on the radiation performance of antennas are examined. Commercially available flexible materials are relatively thin which degrades the bandwidth of HISs. Another practical aspect, which is related to the substrate thickness, is the compactness of the surface. Because of the design limitations of conventional HISs, it is not possible to miniaturize the HIS and increase the bandwidth, simultaneously. To overcome this drawback, a novel HIS is proposed with a periodically perforated ground plane. Copper plated through holes are extremely vulnerable to bending and should be avoided at the bending parts of flexible circuits. Fortunately, if designed properly, the perforations on the ground plane may result in suppression of surface waves. Hence, metallic posts can be eliminated without hindering the surface wave suppression properties of HISs.

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Date Created
2013

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Energy-efficient distributed estimation by utilizing a nonlinear amplifier

Description

Distributed estimation uses many inexpensive sensors to compose an accurate estimate of a given parameter. It is frequently implemented using wireless sensor networks. There have been several studies on optimizing power allocation in wireless sensor networks used for distributed estimation,

Distributed estimation uses many inexpensive sensors to compose an accurate estimate of a given parameter. It is frequently implemented using wireless sensor networks. There have been several studies on optimizing power allocation in wireless sensor networks used for distributed estimation, the vast majority of which assume linear radio-frequency amplifiers. Linear amplifiers are inherently inefficient, so in this dissertation nonlinear amplifiers are examined to gain efficiency while operating distributed sensor networks. This research presents a method to boost efficiency by operating the amplifiers in the nonlinear region of operation. Operating amplifiers nonlinearly presents new challenges. First, nonlinear amplifier characteristics change across manufacturing process variation, temperature, operating voltage, and aging. Secondly, the equations conventionally used for estimators and performance expectations in linear amplify-and-forward systems fail. To compensate for the first challenge, predistortion is utilized not to linearize amplifiers but rather to force them to fit a common nonlinear limiting amplifier model close to the inherent amplifier performance. This minimizes the power impact and the training requirements for predistortion. Second, new estimators are required that account for transmitter nonlinearity. This research derives analytically and confirms via simulation new estimators and performance expectation equations for use in nonlinear distributed estimation. An additional complication when operating nonlinear amplifiers in a wireless environment is the influence of varied and potentially unknown channel gains. The impact of these varied gains and both measurement and channel noise sources on estimation performance are analyzed in this paper. Techniques for minimizing the estimate variance are developed. It is shown that optimizing transmitter power allocation to minimize estimate variance for the most-compressed parameter measurement is equivalent to the problem for linear sensors. Finally, a method for operating distributed estimation in a multipath environment is presented that is capable of developing robust estimates for a wide range of Rician K-factors. This dissertation demonstrates that implementing distributed estimation using nonlinear sensors can boost system efficiency and is compatible with existing techniques from the literature for boosting efficiency at the system level via sensor power allocation. Nonlinear transmitters work best when channel gains are known and channel noise and receiver noise levels are low.

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Date Created
2013

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Energy and quality-aware multimedia signal processing

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Today's mobile devices have to support computation-intensive multimedia applications with a limited energy budget. In this dissertation, we present architecture level and algorithm-level techniques that reduce energy consumption of these devices with minimal impact on system quality. First, we present

Today's mobile devices have to support computation-intensive multimedia applications with a limited energy budget. In this dissertation, we present architecture level and algorithm-level techniques that reduce energy consumption of these devices with minimal impact on system quality. First, we present novel techniques to mitigate the effects of SRAM memory failures in JPEG2000 implementations operating in scaled voltages. We investigate error control coding schemes and propose an unequal error protection scheme tailored for JPEG2000 that reduces overhead without affecting the performance. Furthermore, we propose algorithm-specific techniques for error compensation that exploit the fact that in JPEG2000 the discrete wavelet transform outputs have larger values for low frequency subband coefficients and smaller values for high frequency subband coefficients. Next, we present use of voltage overscaling to reduce the data-path power consumption of JPEG codecs. We propose an algorithm-specific technique which exploits the characteristics of the quantized coefficients after zig-zag scan to mitigate errors introduced by aggressive voltage scaling. Third, we investigate the effect of reducing dynamic range for datapath energy reduction. We analyze the effect of truncation error and propose a scheme that estimates the mean value of the truncation error during the pre-computation stage and compensates for this error. Such a scheme is very effective for reducing the noise power in applications that are dominated by additions and multiplications such as FIR filter and transform computation. We also present a novel sum of absolute difference (SAD) scheme that is based on most significant bit truncation. The proposed scheme exploits the fact that most of the absolute difference (AD) calculations result in small values, and most of the large AD values do not contribute to the SAD values of the blocks that are selected. Such a scheme is highly effective in reducing the energy consumption of motion estimation and intra-prediction kernels in video codecs. Finally, we present several hybrid energy-saving techniques based on combination of voltage scaling, computation reduction and dynamic range reduction that further reduce the energy consumption while keeping the performance degradation very low. For instance, a combination of computation reduction and dynamic range reduction for Discrete Cosine Transform shows on average, 33% to 46% reduction in energy consumption while incurring only 0.5dB to 1.5dB loss in PSNR.

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2012

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Energy efficient RF transmitter design using enhanced breakdown voltage SOI-CMOS compatible MESFETs

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The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of

The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.

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2012

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Efficient test strategies for Analog/RF circuits

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Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order

Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.

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2012

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Mechanics of silicon electrodes in lithium ion batteries

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As one of the most promising materials for high capacity electrode in next generation of lithium ion batteries, silicon has attracted a great deal of attention in recent years. Advanced characterization techniques and atomic simulations helped to depict that the

As one of the most promising materials for high capacity electrode in next generation of lithium ion batteries, silicon has attracted a great deal of attention in recent years. Advanced characterization techniques and atomic simulations helped to depict that the lithiation/delithiation of silicon electrode involves processes including large volume change (anisotropic for the initial lithiation of crystal silicon), plastic flow or softening of material dependent on composition, electrochemically driven phase transformation between solid states, anisotropic or isotropic migration of atomic sharp interface, and mass diffusion of lithium atoms. Motivated by the promising prospect of the application and underlying interesting physics, mechanics coupled with multi-physics of silicon electrodes in lithium ion batteries is studied in this dissertation. For silicon electrodes with large size, diffusion controlled kinetics is assumed, and the coupled large deformation and mass transportation is studied. For crystal silicon with small size, interface controlled kinetics is assumed, and anisotropic interface reaction is studied, with a geometry design principle proposed. As a preliminary experimental validation, enhanced lithiation and fracture behavior of silicon pillars via atomic layer coatings and geometry design is studied, with results supporting the geometry design principle we proposed based on our simulations. Through the work documented here, a consistent description and understanding of the behavior of silicon electrode is given at continuum level and some insights for the future development of the silicon electrode are provided.

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2014