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Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands.

The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.

A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.

Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
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Description
Flexible conducting materials have been in the forefront of a rapidly transforming electronics industry, focusing on wearable devices for a variety of applications in recent times. Over the past few decades, bulky, rigid devices have been replaced with a surging demand for thin, flexible, light weight, ultra-portable yet high performance

Flexible conducting materials have been in the forefront of a rapidly transforming electronics industry, focusing on wearable devices for a variety of applications in recent times. Over the past few decades, bulky, rigid devices have been replaced with a surging demand for thin, flexible, light weight, ultra-portable yet high performance electronics. The interconnects available in the market today only satisfy a few of the desirable characteristics, making it necessary to compromise one feature over another. In this thesis, a method to prepare a thin, flexible, and stretchable inter-connect is presented with improved conductivity compared to previous achievements. It satisfies most mechanical and electrical conditions desired in the wearable electronics industry. The conducting composite, prepared with the widely available, low cost silicon-based organic polymer - polydimethylsiloxane (PDMS) and silver (Ag), is sandwiched between two cured PDMS layers. These protective layers improve the mechanical stability of the inter-connect. The structure can be stretched up to 120% of its original length which can further be enhanced to over 250% by cutting it into a serpentine shape without compromising its electrical stability. The inter-connect, around 500 µm thick, can be integrated into thin electronic packaging. The synthesis process of the composite material, along with its electrical and mechanical and properties are presented in detail. Testing methods and results for mechanical and electrical stability are also illustrated over extensive flexing and stretching cycles. The materials put into test, along with conductive silver (Ag) - polydimethylsiloxane (PDMS) composite in a sandwich structure, are copper foils, copper coated polyimide (PI) and aluminum (Al) coated polyethylene terephthalate (PET).
ContributorsNandy, Mayukh (Author) / Yu, Hongbin (Thesis advisor) / Chan, Candace (Committee member) / Jiang, Hanqing (Committee member) / Arizona State University (Publisher)
Created2020