Matching Items (3)

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Synthesis of Highly Conductive Stretchable Interconnect with Polymer Composite and its Evaluation Against Market-Available Materials

Description

Flexible conducting materials have been in the forefront of a rapidly transforming electronics industry, focusing on wearable devices for a variety of applications in recent times. Over the past few

Flexible conducting materials have been in the forefront of a rapidly transforming electronics industry, focusing on wearable devices for a variety of applications in recent times. Over the past few decades, bulky, rigid devices have been replaced with a surging demand for thin, flexible, light weight, ultra-portable yet high performance electronics. The interconnects available in the market today only satisfy a few of the desirable characteristics, making it necessary to compromise one feature over another. In this thesis, a method to prepare a thin, flexible, and stretchable inter-connect is presented with improved conductivity compared to previous achievements. It satisfies most mechanical and electrical conditions desired in the wearable electronics industry. The conducting composite, prepared with the widely available, low cost silicon-based organic polymer - polydimethylsiloxane (PDMS) and silver (Ag), is sandwiched between two cured PDMS layers. These protective layers improve the mechanical stability of the inter-connect. The structure can be stretched up to 120% of its original length which can further be enhanced to over 250% by cutting it into a serpentine shape without compromising its electrical stability. The inter-connect, around 500 µm thick, can be integrated into thin electronic packaging. The synthesis process of the composite material, along with its electrical and mechanical and properties are presented in detail. Testing methods and results for mechanical and electrical stability are also illustrated over extensive flexing and stretching cycles. The materials put into test, along with conductive silver (Ag) - polydimethylsiloxane (PDMS) composite in a sandwich structure, are copper foils, copper coated polyimide (PI) and aluminum (Al) coated polyethylene terephthalate (PET).

Contributors

Agent

Created

Date Created
  • 2020

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Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

Description

The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are

The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.

A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.

Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.

Contributors

Agent

Created

Date Created
  • 2018

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Electromigration in gold interconnects

Description

Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization

Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.

Contributors

Agent

Created

Date Created
  • 2013