Matching Items (2)

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The value of a STEM PhD

Description

The quality and quantity of talented members of the US STEM workforce has

been a subject of great interest to policy and decision makers for the past 40 years.

Recent research indicates

The quality and quantity of talented members of the US STEM workforce has

been a subject of great interest to policy and decision makers for the past 40 years.

Recent research indicates that while there exist specific shortages in specific disciplines

and areas of expertise in the private sector and the federal government, there is no

noticeable shortage in any STEM academic discipline, but rather a surplus of PhDs

vying for increasingly scarce tenure track positions. Despite the seeming availability

of industry and private sector jobs, recent PhDs still struggle to find employment in

those areas. I argue that the decades old narrative suggesting a shortage of STEM

PhDs in the US poses a threat to the value of the natural science PhD, and that

this narrative contributes significantly to why so many PhDs struggle to find career

employment in their fields. This study aims to address the following question: what is

the value of a STEM PhD outside academia? I begin with a critical review of existing

literature, and then analyze programmatic documents for STEM PhD programs at

ASU, interviews with industry employers, and an examination the public face of value

for these degrees. I then uncover the nature of the value alignment, value disconnect,

and value erosion in the ecosystem which produces and then employs STEM PhDs,

concluding with specific areas which merit special consideration in an effort to increase

the value of these degrees for all stakeholders involved.

Contributors

Agent

Created

Date Created
  • 2018

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System-level synthesis of dataplane subsystems for MPSoCs

Description

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.

Contributors

Agent

Created

Date Created
  • 2013