Matching Items (3)

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FPGA-based implementation of QR decomposition

Description

This thesis report aims at introducing the background of QR decomposition and its application. QR decomposition using Givens rotations is a efficient method to prevent directly matrix inverse in solving least square minimization problem, which is a typical approach for

This thesis report aims at introducing the background of QR decomposition and its application. QR decomposition using Givens rotations is a efficient method to prevent directly matrix inverse in solving least square minimization problem, which is a typical approach for weight calculation in adaptive beamforming. Furthermore, this thesis introduces Givens rotations algorithm and two general VLSI (very large scale integrated circuit) architectures namely triangular systolic array and linear systolic array for numerically QR decomposition. To fulfill the goal, a 4 input channels triangular systolic array with 16 bits fixed-point format and a 5 input channels linear systolic array are implemented on FPGA (Field programmable gate array). The final result shows that the estimated clock frequencies of 65 MHz and 135 MHz on post-place and route static timing report could be achieved using Xilinx Virtex 6 xc6vlx240t chip. Meanwhile, this report proposes a new method to test the dynamic range of QR-D. The dynamic range of the both architectures can be achieved around 110dB.

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Date Created
2014

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Performance analysis of MIMO relay networks with beamforming

Description

This dissertation considers two different kinds of two-hop multiple-input multiple-output (MIMO) relay networks with beamforming (BF). First, "one-way" amplify-and-forward (AF) and decode-and-forward (DF) MIMO BF relay networks are considered, in which the relay amplifies or decodes the received signal from

This dissertation considers two different kinds of two-hop multiple-input multiple-output (MIMO) relay networks with beamforming (BF). First, "one-way" amplify-and-forward (AF) and decode-and-forward (DF) MIMO BF relay networks are considered, in which the relay amplifies or decodes the received signal from the source and forwards it to the destination, respectively, where all nodes beamform with multiple antennas to obtain gains in performance with reduced power consumption. A direct link from source to destination is included in performance analysis. Novel systematic upper-bounds and lower-bounds to average bit or symbol error rates (BERs or SERs) are proposed. Second, "two-way" AF MIMO BF relay networks are investigated, in which two sources exchange their data through a relay, to improve the spectral efficiency compared with one-way relay networks. Novel unified performance analysis is carried out for five different relaying schemes using two, three, and four time slots in sum-BER, the sum of two BERs at both sources, in two-way relay networks with and without direct links. For both kinds of relay networks, when any node is beamforming simultaneously to two nodes (i.e. from source to relay and destination in one-way relay networks, and from relay to both sources in two-way relay networks), the selection of the BF coefficients at a beamforming node becomes a challenging problem since it has to balance the needs of both receiving nodes. Although this "BF optimization" is performed for BER, SER, and sum-BER in this dissertation, the solution for optimal BF coefficients not only is difficult to implement, it also does not lend itself to performance analysis because the optimal BF coefficients cannot be expressed in closed-form. Therefore, the performance of optimal schemes through bounds, as well as suboptimal ones such as strong-path BF, which beamforms to the stronger path of two links based on their received signal-to-noise ratios (SNRs), is provided for BERs or SERs, for the first time. Since different channel state information (CSI) assumptions at the source, relay, and destination provide different error performance, various CSI assumptions are also considered.

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Date Created
2012

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Algorithm and Hardware Design for High Volume Rate 3-D Medical Ultrasound Imaging

Description

Ultrasound B-mode imaging is an increasingly significant medical imaging modality for clinical applications. Compared to other imaging modalities like computed tomography (CT) or magnetic resonance imaging (MRI), ultrasound imaging has the advantage of being safe, inexpensive, and portable. While two

Ultrasound B-mode imaging is an increasingly significant medical imaging modality for clinical applications. Compared to other imaging modalities like computed tomography (CT) or magnetic resonance imaging (MRI), ultrasound imaging has the advantage of being safe, inexpensive, and portable. While two dimensional (2-D) ultrasound imaging is very popular, three dimensional (3-D) ultrasound imaging provides distinct advantages over its 2-D counterpart by providing volumetric imaging, which leads to more accurate analysis of tumor and cysts. However, the amount of received data at the front-end of 3-D system is extremely large, making it impractical for power-constrained portable systems.

In this thesis, algorithm and hardware design techniques to support a hand-held 3-D ultrasound imaging system are proposed. Synthetic aperture sequential beamforming (SASB) is chosen since its computations can be split into two stages, where the output generated of Stage 1 is significantly smaller in size compared to the input. This characteristic enables Stage 1 to be done in the front end while Stage 2 can be sent out to be processed elsewhere.

The contributions of this thesis are as follows. First, 2-D SASB is extended to 3-D. Techniques to increase the volume rate of 3-D SASB through a new multi-line firing scheme and use of linear chirp as the excitation waveform, are presented. A new sparse array design that not only reduces the number of active transducers but also avoids the imaging degradation caused by grating lobes, is proposed. A combination of these techniques increases the volume rate of 3-D SASB by 4\texttimes{} without introducing extra computations at the front end.

Next, algorithmic techniques to further reduce the Stage 1 computations in the front end are presented. These include reducing the number of distinct apodization coefficients and operating with narrow-bit-width fixed-point data. A 3-D die stacked architecture is designed for the front end. This highly parallel architecture enables the signals received by 961 active transducers to be digitalized, routed by a network-on-chip, and processed in parallel. The processed data are accumulated through a bus-based structure. This architecture is synthesized using TSMC 28 nm technology node and the estimated power consumption of the front end is less than 2 W.

Finally, the Stage 2 computations are mapped onto a reconfigurable multi-core architecture, TRANSFORMER, which supports different types of on-chip memory banks and run-time reconfigurable connections between general processing elements and memory banks. The matched filtering step and the beamforming step in Stage 2 are mapped onto TRANSFORMER with different memory configurations. Gem5 simulations show that the private cache mode generates shorter execution time and higher computation efficiency compared to other cache modes. The overall execution time for Stage 2 is 14.73 ms. The average power consumption and the average Giga-operations-per-second/Watt in 14 nm technology node are 0.14 W and 103.84, respectively.

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Date Created
2019