Output bandwidth limitations of basestation power amplifier design and its implementation using Doherty amplifier
This thesis is a study of Bandwidth limitation of basestation power amplifier and its Doherty application. Fundamentally, bandwidth of a power amplifier (PA) is limited by both its input and output prematch networks and its Doherty architecture, specifically the impedance inverter between the main and auxiliary amplifier. In this study, only the output prematch network and the Doherty architecture follows are being investigated. A new proposed impedance inverter in the Doherty architecture exhibits an extended bandwidth compared to traditional quarterwave line.
Base on the loadline analysis, output impedance of the power amplifier can be represented by a loadline resistor and an output shunt capacitor. Base on this simple model, the maximum allowed bandwidth of the output impedance of the power amplifier can be estimated using the Bode-Fano method. However, since power amplifier is in fact nonlinear, harmonic balance simulation is used to loadpull the device across a broad range of frequencies. Base on the simulated large signal impedance at maximum power, the prematch circuitry can be designed. On a system level, the prematch power amplifier is used in Doherty amplifier. Two different prematch circuitries, T- section and shunt L methods are investigated along with their comparison in the Doherty architecture at both back off power and peak power condition. The last section of the thesis will be incorporating the proposed impedance inverter structure between the main and auxiliary amplifiers.
The simulated results showed the shunt L prematch topology has the least impedance dispersion across frequency. Along with the new impedance inverter structure, the 65% efficiency bandwidth improves by 50% compared to the original impedance inverter structure at back off power level.