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- Genre: Masters Thesis
- Creators: Arizona State University
- Creators: Chakraborty, Bijeta
- Creators: Peterson, Cory
- Member of: ASU Electronic Theses and Dissertations
Description
Linear Temporal Logic is gaining increasing popularity as a high level specification language for robot motion planning due to its expressive power and scalability of LTL control synthesis algorithms. This formalism, however, requires expert knowledge and makes it inaccessible to non-expert users. This thesis introduces a graphical specification environment to create high level motion plans to control robots in the field by converting a visual representation of the motion/task plan into a Linear Temporal Logic (LTL) specification. The visual interface is built on the Android tablet platform and provides functionality to create task plans through a set of well defined gestures and on screen controls. It uses the notion of waypoints to quickly and efficiently describe the motion plan and enables a variety of complex Linear Temporal Logic specifications to be described succinctly and intuitively by the user without the need for the knowledge and understanding of LTL specification. Thus, it opens avenues for its use by personnel in military, warehouse management, and search and rescue missions. This thesis describes the construction of LTL for various scenarios used for robot navigation using the visual interface developed and leverages the use of existing LTL based motion planners to carry out the task plan by a robot.
ContributorsSrinivas, Shashank (Author) / Fainekos, Georgios (Thesis advisor) / Baral, Chitta (Committee member) / Burleson, Winslow (Committee member) / Arizona State University (Publisher)
Created2013
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis is focused on the study of wind energy integration and is divided into two segments. The first part of the thesis deals with developing a reliability evaluation technique for a wind integrated power system. A multiple-partial outage model is utilized to accurately calculate the wind generation availability. A methodology is presented to estimate the outage probability of wind generators while incorporating their reduced power output levels at low wind speeds. Subsequently, power system reliability is assessed by calculating the loss of load probability (LOLP) and the effect of wind integration on the overall system is analyzed. Actual generation and load data of the Texas power system in 2008 are used to construct a test case. To demonstrate the robustness of the method, relia-bility studies have been conducted for a fairly constant as well as for a largely varying wind generation profile. Further, the case of increased wind generation penetration level has been simulated and comments made about the usability of the proposed method to aid in power system planning in scenarios of future expansion of wind energy infrastructure. The second part of this thesis explains the development of a graphic user interface (GUI) to demonstrate the operation of a grid connected doubly fed induction generator (DFIG). The theory of DFIG and its back-to-back power converter is described. The GUI illustrates the power flow, behavior of the electrical circuit and the maximum power point tracking of the machine for a variable wind speed input provided by the user. The tool, although developed on MATLAB software platform, has been constructed to work as a standalone application on Windows operating system based computer and enables even the non-engineering students to access it. Results of both the segments of the thesis are discussed. Remarks are presented about the validity of the reliability technique and GUI interface for variable wind speed conditions. Improvements have been suggested to enable the use of the reliability technique for a more elaborate system. Recommendations have been made about expanding the features of the GUI tool and to use it to promote educational interest about renewable power engineering.
ContributorsSinha, Anubhav (Author) / Heydt, Gerald T (Thesis advisor) / Vittal, Vijay (Thesis advisor) / Ayyanar, Raja (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2012
Description
With increased usage of green energy, the number of photovoltaic arrays used in power generation is increasing rapidly. Many of the arrays are located at remote locations where faults that occur within the array often go unnoticed and unattended for large periods of time. Technicians sent to rectify the faults have to spend a large amount of time determining the location of the fault manually. Automated monitoring systems are needed to obtain the information about the performance of the array and detect faults. Such systems must monitor the DC side of the array in addition to the AC side to identify non catastrophic faults. This thesis focuses on two of the requirements for DC side monitoring of an automated PV array monitoring system. The first part of the thesis quantifies the advantages of obtaining higher resolution data from a PV array on detection of faults. Data for the monitoring system can be gathered for the array as a whole or from additional places within the array such as individual modules and end of strings. The fault detection rate and the false positive rates are compared for array level, string level and module level PV data. Monte Carlo simulations are performed using PV array models developed in Simulink and MATLAB for fault and no fault cases. The second part describes a graphical user interface (GUI) that can be used to visualize the PV array for module level monitoring system information. A demonstration GUI is built in MATLAB using data obtained from a PV array test facility in Tempe, AZ. Visualizations are implemented to display information about the array as a whole or individual modules and locate faults in the array.
ContributorsKrishnan, Venkatachalam (Author) / Tepedelenlioğlu, Cihan (Thesis advisor) / Spanias, Andreas (Thesis advisor) / Ayyanar, Raja (Committee member) / Papandreou-Suppappola, Antonia (Committee member) / Arizona State University (Publisher)
Created2012
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
In this thesis, a digital input class D audio amplifier system which has the ability
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.
Based on simulation, the power supply rejection at 200Hz is about -49dB with
81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
ContributorsBai, Jing (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2015
Description
Robots are becoming an important part of our life and industry. Although a lot of robot control interfaces have been developed to simplify the control method and improve user experience, users still cannot control robots comfortably. With the improvements of the robot functions, the requirements of universality and ease of use of robot control interfaces are also increasing. This research introduces a graphical interface for Linear Temporal Logic (LTL) specifications for mobile robots. It is a sketch based interface built on the Android platform which makes the LTL control interface more friendly to non-expert users. By predefining a set of areas of interest, this interface can quickly and efficiently create plans that satisfy extended plan goals in LTL. The interface can also allow users to customize the paths for this plan by sketching a set of reference trajectories. Given the custom paths by the user, the LTL specification and the environment, the interface generates a plan balancing the customized paths and the LTL specifications. We also show experimental results with the implemented interface.
ContributorsWei, Wei (Author) / Fainekos, Georgios (Thesis advisor) / Amor, Hani Ben (Committee member) / Zhang, Yu (Committee member) / Arizona State University (Publisher)
Created2016