Matching Items (4)
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- All Subjects: Audio amplifiers
- All Subjects: Audio amplifiers--Design and construction.
- All Subjects: Gain enhancement
- Creators: Song, Hongjiang
- Creators: Chakraborty, Bijeta
- Creators: Peterson, Cory
- Member of: ASU Electronic Theses and Dissertations
- Status: Published
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones. Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently.
In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology.
In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology.
ContributorsJing, Yue (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2017