Matching Items (3)
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- All Subjects: Integrated circuits
- Creators: Schroder, Dieter
- Creators: Chawla, Nikhilesh
Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
Description
Over the past several years, the density of integrated circuits has been increasing at a very fast rate, following Moore’s law. The advent of three dimensional (3D) packaging technologies enable the increase in density of integrated circuits without necessarily shrinking the dimensions of the device. Under such constraints, the solder volume necessary to join the various layers of the package is also extremely small. At smaller length scales, the local cooling rates are higher, so the microstructures are much finer than that obtained in larger joints (BGA, C4). The fraction of intermetallic compounds (IMCs) present in solder joints in these volumes will be larger. The Cu6Sn5 precipitate size and spacing, and Sn grain structure and crystallography will be different at very small volumes. These factors will most certainly affect the performance of the solder. Examining the mechanical behavior and reliability of Pb-free solders is difficult, primarily because a methodology to characterize the microstructure and the mechanics of deformation at these extremely small length scales has yet to be developed.
In this study, Sn grain orientation and Cu6Sn5 IMC fraction, size, and morphology are characterized in 3D, in pure Sn based solder joints. The obtained results show differences in morphology of Sn grains and IMC precipitates as a function of location within the solder joint indicating influence of local cooling rate differences. Ex situ and in situ electromigration tests done on 250 um and 500 um pure Sn solder joints elucidate the evolution of microstructure, specifically Sn grain growth, IMC segregation and surface degradation. This research implements 3D quantification of microstructural features over micro and nano-scales, thereby enabling a multi-scale / multi-characterization approach.
In this study, Sn grain orientation and Cu6Sn5 IMC fraction, size, and morphology are characterized in 3D, in pure Sn based solder joints. The obtained results show differences in morphology of Sn grains and IMC precipitates as a function of location within the solder joint indicating influence of local cooling rate differences. Ex situ and in situ electromigration tests done on 250 um and 500 um pure Sn solder joints elucidate the evolution of microstructure, specifically Sn grain growth, IMC segregation and surface degradation. This research implements 3D quantification of microstructural features over micro and nano-scales, thereby enabling a multi-scale / multi-characterization approach.
ContributorsKirubanandham, Antony (Author) / Chawla, Nikhilesh (Thesis advisor) / Jiao, Yang (Committee member) / Lu, Minhua (Committee member) / Rajagopalan, Jagannathan (Committee member) / Arizona State University (Publisher)
Created2016