Matching Items (4)
Filtering by
- Genre: Masters Thesis
Description
Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
ContributorsMagod Ramakrishna, Raveesh (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
This thesis dissertation presents design of portable low power Electrochemical Impedance Spectroscopy (EIS) system which can be used for biomedical applications such as tear diagnosis, blood diagnosis, or any other body-fluid diagnosis. Two design methodologies are explained in this dissertation (a) a discrete component-based portable low-power EIS system and (b) an integrated CMOS-based portable low-power EIS system. Both EIS systems were tested in a laboratory environment and the characterization results are compared. The advantages and disadvantages of the integrated EIS system relative to the discrete component-based EIS system are presented including experimental data. The specifications of both EIS systems are compared with commercially available non-portable EIS workstations. These designed EIS systems are handheld and very low-cost relative to the currently available commercial EIS workstations.
ContributorsGhorband, Vishal (Author) / Blain Christen, Jennifer (Thesis advisor) / Song, Hongjiang (Committee member) / LaBelle, Jeffrey (Committee member) / Arizona State University (Publisher)
Created2016
Description
In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24]. First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area. Our implementation of the 2D DCT has comparable PSNR performance with respect to the algorithm presented in [23] with ~35-50% reduction in area. Next, we use the approximate 2x2 multiplier presented in [24] to implement parallel approximate multipliers. We demonstrate that if some of the 2x2 multipliers in the design of the parallel multiplier are accurate, the accuracy of the multiplier improves significantly, especially when two large numbers are multiplied. We choose Gaussian FIR Filter and Fast Fourier Transform (FFT) algorithms to illustrate the efficacy of our proposed approximate multiplier. We show that application of the proposed approximate multiplier improves the PSNR performance of 32x32 FFT implementation by 4.7 dB compared to the implementation using the approximate multiplier described in [24]. We also implement a state-of-the-art image enlargement algorithm, namely Segment Adaptive Gradient Angle (SAGA) [29], in hardware. The algorithm is mapped to pipelined hardware blocks and we synthesized the design using 90 nm technology. We show that a 64x64 image can be processed in 496.48 µs when clocked at 100 MHz. The average PSNR performance of our implementation using accurate parallel adders and multipliers is 31.33 dB and that using approximate parallel adders and multipliers is 30.86 dB, when evaluated against the original image. The PSNR performance of both designs is comparable to the performance of the double precision floating point MATLAB implementation of the algorithm.
ContributorsVasudevan, Madhu (Author) / Chakrabarti, Chaitali (Thesis advisor) / Frakes, David (Committee member) / Gupta, Sandeep (Committee member) / Arizona State University (Publisher)
Created2013
Description
Technological advances in low power wearable electronics and energy optimization techniques
make motion energy harvesting a viable energy source. However, it has not been
widely adopted due to bulky energy harvester designs that are uncomfortable to wear. This
work addresses this problem by analyzing the feasibility of powering low wearable power
devices using piezoelectric energy generated at the human knee. We start with a novel
mathematical model for estimating the power generated from human knee joint movements.
This thesis’s major contribution is to analyze the feasibility of human motion energy harvesting
and validating this analytical model using a commercially available piezoelectric
module. To this end, we implemented an experimental setup that replicates a human knee.
Then, we performed experiments at different excitation frequencies and amplitudes with
two commercially available Macro Fiber Composite (MFC) modules. These experimental
results are used to validate the analytical model and predict the energy harvested as a function
of the number of steps taken in a day. The model estimates that 13μWcan be generated
on an average while walking with a 4.8% modeling error. The obtained results show that
piezoelectricity is indeed a viable approach for powering low-power wearable devices.
make motion energy harvesting a viable energy source. However, it has not been
widely adopted due to bulky energy harvester designs that are uncomfortable to wear. This
work addresses this problem by analyzing the feasibility of powering low wearable power
devices using piezoelectric energy generated at the human knee. We start with a novel
mathematical model for estimating the power generated from human knee joint movements.
This thesis’s major contribution is to analyze the feasibility of human motion energy harvesting
and validating this analytical model using a commercially available piezoelectric
module. To this end, we implemented an experimental setup that replicates a human knee.
Then, we performed experiments at different excitation frequencies and amplitudes with
two commercially available Macro Fiber Composite (MFC) modules. These experimental
results are used to validate the analytical model and predict the energy harvested as a function
of the number of steps taken in a day. The model estimates that 13μWcan be generated
on an average while walking with a 4.8% modeling error. The obtained results show that
piezoelectricity is indeed a viable approach for powering low-power wearable devices.
ContributorsBandyopadhyay, Shiva (Author) / Ogras, Umit Y. (Thesis advisor) / Fan, Deliang (Committee member) / Trichopoulos, Georgios (Committee member) / Arizona State University (Publisher)
Created2020