Matching Items (4)

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Infinite cacheflow: a rule-caching solution for software defined networks

Description

New OpenFlow switches support a wide range of network applications, such as firewalls, load balancers, routers, and traffic monitoring. While ternary content addressable memory (TCAM) allows switches to process packets

New OpenFlow switches support a wide range of network applications, such as firewalls, load balancers, routers, and traffic monitoring. While ternary content addressable memory (TCAM) allows switches to process packets at high speed based on multiple header fields, today's commodity switches support just thousands to tens of thousands of forwarding rules. To allow for finer-grained policies on this hardware, efficient ways to support the abstraction of a switch are needed with arbitrarily large rule tables. To do so, a hardware-software hybrid switch is designed that relies on rule caching to provide large rule tables at low cost. Unlike traditional caching solutions, neither individual rules are cached (to respect rule dependencies) nor compressed (to preserve the per-rule traffic counts). Instead long dependency chains are ``spliced'' to cache smaller groups of rules while preserving the semantics of the network policy. The proposed hybrid switch design satisfies three criteria: (1) responsiveness, to allow rapid changes to the cache with minimal effect on traffic throughput; (2) transparency, to faithfully support native OpenFlow semantics; (3) correctness, to cache rules while preserving the semantics of the original policy. The evaluation of the hybrid switch on large rule tables suggest that it can effectively expose the benefits of both hardware and software switches to the controller and to applications running on top of it.

Contributors

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Created

Date Created
  • 2014

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Efficient circuit analysis under multiple input switching (MIS)

Description

Characterization of standard cells is one of the crucial steps in the IC design. Scaling of CMOS technology has lead to timing un-certainties such as that of cross coupling noise

Characterization of standard cells is one of the crucial steps in the IC design. Scaling of CMOS technology has lead to timing un-certainties such as that of cross coupling noise due to interconnect parasitic, skew variation due to voltage jitter and proximity effect of multiple inputs switching (MIS). Due to increased operating frequency and process variation, the probability of MIS occurrence and setup / hold failure within a clock cycle is high. The delay variation due to temporal proximity of MIS is significant for multiple input gates in the standard cell library. The shortest paths are affected by MIS due to the lack of averaging effect. Thus, sensitive designs such as that of SRAM row and column decoder circuits have high probability for MIS impact. The traditional static timing analysis (STA) assumes single input switching (SIS) scenario which is not adequate enough to capture gate delay accurately, as the delay variation due to temporal proximity of the MIS is ~15%-45%. Whereas, considering all possible scenarios of MIS for characterization is computationally intensive with huge data volume. Various modeling techniques are developed for the characterization of MIS effect. Some techniques require coefficient extraction through multiple spice simulation, and do not discuss speed up approach or apply models with complicated algorithms to account for MIS effect. The STA flow accounts for process variation through uncertainty parameter to improve product yield. Some of the MIS delay variability models account for MIS variation through table look up approach, resulting in huge data volume or do not consider propagation of RAT in the design flow. Thus, there is a need for a methodology to model MIS effect with less computational resource, and integration of such effect into design flow without trading off the accuracy. A finite-point based analytical model for MIS effect is proposed for multiple input logic gates and similar approach is extended for setup/hold characterization of sequential elements. Integration of MIS variation into design flow is explored. The proposed methodology is validated using benchmark circuits at 45nm technology node under process variation. Experimental results show significant reduction in runtime and data volume with ~10% error compared to that of SPICE simulation.

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Created

Date Created
  • 2012

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Voice over LTE study and test strategy definition

Description

Voice and other circuit switched services in a LTE deployment can be based on a Circuit Switched Fall Back mechanism or on the upcoming Voice Over LTE option. Voice Over

Voice and other circuit switched services in a LTE deployment can be based on a Circuit Switched Fall Back mechanism or on the upcoming Voice Over LTE option. Voice Over LTE option can be used with its SIP based signaling to route voice calls and other circuit switched services over the LTE's packet switched core. The main issue that is faced though is the validation of this approach before the deployment over commercial network. The test strategy devised as a result of this work will be able to visit corner scenarios and error sensitive services, so that signaling involved can be verified to ensure a robust deployment of the Voice Over LTE network. Signaling test strategy is based on the observations made during a simulated Voice Over LTE call inside the lab in a controlled environment. Emergency services offered are carefully studied to devise a robust test strategy to make sure that any service failure is avoided. Other area were the service is routed via different protocol stack layer than it normally is in a legacy circuit switched core are identified and brought into the scope of the test strategy.

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Created

Date Created
  • 2014

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Characterization of copper-doped silicon dioxide programmable metallization cells

Description

Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of

Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of these cations. This dissertation presents electrical characterization results on Cu-SiO2 based PMC devices, which due to the na- ture of materials can be easily integrated into the current Complimentary metal oxide semiconductor (CMOS) process line. Device structures representing individual mem- ory cells based on W bottom electrode and n-type Si bottom electrode were fabricated for characterization. For the W bottom electrode based devices, switching was ob- served for voltages in the range of 500mV and current value as low as 100 nA showing the electrochemical nature and low power potential. The ON state showed a direct de- pendence on the programming current, showing the possibility of multi-bit storage in a single cell. Room temperature retention was demonstrated in excess of 105 seconds and endurance to approximately 107 cycles. Switching was observed for microsecond duration 3 V amplitude pulses. Material characterization results from Raman, X-ray diffraction, Rutherford backscattering and Secondary-ion mass spectroscopy analysis shows the influence of processing conditions on the Cu concentration within the film and also the presence of Cu as free atoms. The results seemed to indicate stress-induced void formation in the SiO2 matrix as the driving mechanism for Cu diffusion into the SiO2 film. Cu/SiO2
Si based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode.

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Created

Date Created
  • 2011