Matching Items (9)

Simulation models for programmable metallization cells

Description

Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also

Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also having minimal physical size, energy usage, and cost. The programmable metallization cell (PMC) is an emerging memory technology that is likely to surpass flash memory in all the listed ideal memory characteristics. A comprehensive physics-based model is needed to fully understand PMC operation and aid in design optimization. With the intent of advancing the PMC modeling effort, this thesis presents two simulation models for the PMC. The first model is a finite element model based on Silvaco Atlas finite element analysis software. Limitations of the software are identified that make this model inconsistent with the operating mechanism of the PMC. The second model is a physics-based numerical model developed for the PMC. This model is successful in matching data measured from a chalcogenide glass PMC designed and manufactured at ASU. Matched operating characteristics observable in the current and resistance vs. voltage data include the OFF/ON resistances and write/erase and electrodeposition voltage thresholds. Multilevel programming is also explained and demonstrated with the numerical model. The numerical model has already proven useful by revealing some information presented about the operation and characteristics of the PMC.

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Date Created
  • 2013

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Static behavior of chalcogenide based programmable metallization cells

Description

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization.

To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.

The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.

The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.

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Date Created
  • 2014

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Cu-Silica Based Programmable Metallization Cell: Fabrication, Characterization and Applications

Description

The Programmable Metallization Cell (PMC) is a novel solid-state resistive switching technology. It has a simple metal-insulator-metal “MIM” structure with one metal being electrochemically active (Cu) and the other one

The Programmable Metallization Cell (PMC) is a novel solid-state resistive switching technology. It has a simple metal-insulator-metal “MIM” structure with one metal being electrochemically active (Cu) and the other one being inert (Pt or W), an insulating film (silica) acts as solid electrolyte for ion transport is sandwiched between these two electrodes. PMC’s resistance can be altered by an external electrical stimulus. The change of resistance is attributed to the formation or dissolution of Cu metal filament(s) within the silica layer which is associated with electrochemical redox reactions and ion transportation. In this dissertation, a comprehensive study of microfabrication method and its impacts on performance of PMC device is demonstrated, gamma-ray total ionizing dose (TID) impacts on device reliability is investigated, and the materials properties of doped/undoped silica switching layers are illuminated by impedance spectroscopy (IS). Due to the inherent CMOS compatibility, Cu-silica PMCs have great potential to be adopted in many emerging technologies, such as non-volatile storage cells and selector cells in ultra-dense 3D crosspoint memories, as well as electronic synapses in brain-inspired neuromorphic computing. Cu-silica PMC device performance for these applications is also assessed in this dissertation.

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Date Created
  • 2017

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Programmable metallization cell devices for flexible electronics

Description

Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between

Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self-healing capability, which depends on the applied healing voltage and the current limit. However, they fail at lower current densities than metal interconnects due to an ion-drift induced failure mechanism. The results on the PMC based switches demonstrate that a model comprising a Schottky diode in parallel with a variable resistor predicts the behavior of the device.

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Date Created
  • 2011

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Multilevel resistance programming in conductive bridge resistive memory

Description

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

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Created

Date Created
  • 2015

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VerilogA modelling of programmable metallization cells

Description

There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied

There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories.

In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation.

A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies.

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Date Created
  • 2014

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Space Radiation Effects in Conductive Bridging Random Access Memory

Description

This work investigates the effects of ionizing radiation and displacement damage on the retention of state, DC programming, and neuromorphic pulsed programming of Ag-Ge30Se70 conductive bridging random access memory (CBRAM)

This work investigates the effects of ionizing radiation and displacement damage on the retention of state, DC programming, and neuromorphic pulsed programming of Ag-Ge30Se70 conductive bridging random access memory (CBRAM) devices. The results show that CBRAM devices are susceptible to both environments. An observable degradation in electrical response due to total ionizing dose (TID) is shown during neuromorphic pulsed programming at TID below 1 Mrad using Cobalt-60. DC cycling in a 14 MeV neutron environment showed a collapse of the high resistance state (HRS) and low resistance state (LRS) programming window after a fluence of 4.9x10^{12} n/cm^2, demonstrating the CBRAM can fail in a displacement damage environment. Heavy ion exposure during retention testing and DC cycling, showed that failures to programming occurred at approximately the same threshold, indicating that the failure mechanism for the two types of tests may be the same. The dose received due to ionizing electronic interactions and non-ionizing kinetic interactions, was calculated for each ion species at the fluence of failure. TID values appear to be the most correlated, indicating that TID effects may be the dominate failure mechanism in a combined environment, though it is currently unclear as to how the displacement damage also contributes to the response. An analysis of material effects due to TID has indicated that radiation damage can limit the migration of Ag+ ions. The reduction in ion current density can explain several of the effects observed in CBRAM while in the LRS.

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Date Created
  • 2018

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Characterization of copper-doped silicon dioxide programmable metallization cells

Description

Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of

Programmable Metallization Cell (PMC) is a resistance-switching device based on migration of nanoscale quantities of cations in a solid electrolyte and formation of a conducting electrodeposit by the reductions of these cations. This dissertation presents electrical characterization results on Cu-SiO2 based PMC devices, which due to the na- ture of materials can be easily integrated into the current Complimentary metal oxide semiconductor (CMOS) process line. Device structures representing individual mem- ory cells based on W bottom electrode and n-type Si bottom electrode were fabricated for characterization. For the W bottom electrode based devices, switching was ob- served for voltages in the range of 500mV and current value as low as 100 nA showing the electrochemical nature and low power potential. The ON state showed a direct de- pendence on the programming current, showing the possibility of multi-bit storage in a single cell. Room temperature retention was demonstrated in excess of 105 seconds and endurance to approximately 107 cycles. Switching was observed for microsecond duration 3 V amplitude pulses. Material characterization results from Raman, X-ray diffraction, Rutherford backscattering and Secondary-ion mass spectroscopy analysis shows the influence of processing conditions on the Cu concentration within the film and also the presence of Cu as free atoms. The results seemed to indicate stress-induced void formation in the SiO2 matrix as the driving mechanism for Cu diffusion into the SiO2 film. Cu/SiO2
Si based PMC devices were characterized and were shown to have inherent isolation characteristics, proving the feasibility of such a structure for a passive array. The inherent isolation property simplifies fabrication by avoiding the need for a separate diode element in an array. The isolation characteristics were studied mainly in terms of the leakage current. The nature of the diode interface was further studied by extracting a barrier potential which shows it can be approximated to a Cu-nSi metal semiconductor Schottky diode.

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Date Created
  • 2011

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Kinetics of programmable metallization cell memory

Description

Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include

Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared.

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Date Created
  • 2011