Matching Items (3)
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- All Subjects: Silicon-on-insulator technology
- Genre: Doctoral Dissertation
- Creators: Goryll, Michael
- Member of: ASU Electronic Theses and Dissertations
Description
In the last few years, significant advances in nanofabrication have allowed tailoring of structures and materials at a molecular level enabling nanofabrication with precise control of dimensions and organization at molecular length scales, a development leading to significant advances in nanoscale systems. Although, the direction of progress seems to follow the path of microelectronics, the fundamental physics in a nanoscale system changes more rapidly compared to microelectronics, as the size scale is decreased. The changes in length, area, and volume ratios due to reduction in size alter the relative influence of various physical effects determining the overall operation of a system in unexpected ways. One such category of nanofluidic structures demonstrating unique ionic and molecular transport characteristics are nanopores. Nanopores derive their unique transport characteristics from the electrostatic interaction of nanopore surface charge with aqueous ionic solutions. In this doctoral research cylindrical nanopores, in single and array configuration, were fabricated in silicon-on-insulator (SOI) using a combination of electron beam lithography (EBL) and reactive ion etching (RIE). The fabrication method presented is compatible with standard semiconductor foundries and allows fabrication of nanopores with desired geometries and precise dimensional control, providing near ideal and isolated physical modeling systems to study ion transport at the nanometer level. Ion transport through nanopores was characterized by measuring ionic conductances of arrays of nanopores of various diameters for a wide range of concentration of aqueous hydrochloric acid (HCl) ionic solutions. Measured ionic conductances demonstrated two distinct regimes based on surface charge interactions at low ionic concentrations and nanopore geometry at high ionic concentrations. Field effect modulation of ion transport through nanopore arrays, in a fashion similar to semiconductor transistors, was also studied. Using ionic conductance measurements, it was shown that the concentration of ions in the nanopore volume was significantly changed when a gate voltage on nanopore arrays was applied, hence controlling their transport. Based on the ion transport results, single nanopores were used to demonstrate their application as nanoscale particle counters by using polystyrene nanobeads, monodispersed in aqueous HCl solutions of different molarities. Effects of field effect modulation on particle transition events were also demonstrated.
ContributorsJoshi, Punarvasu (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Thesis advisor) / Spanias, Andreas (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010