Matching Items (7)
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- All Subjects: Photovoltaic power generation
- Genre: Masters Thesis
- Creators: Bakkaloglu, Bertan
- Creators: Karady, George G.
Description
Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and feature on chip digital mixing. Digital mixing offers many benefits concerning I and Q matching but has one major drawback; the update rate of the DAC must be higher than the intermediate frequency (IF) which is most commonly a factor of 4. This drawback motivates the need for interpolation so that a low update rate can be used for components preceding the DACs. In this thesis the design of an interpolating DAC integrated circuit (IC) to be used in a transmitter application for generating a 100MHz IF is presented. Many of the transistor level implementations are provided. The tradeoffs in the design are analyzed and various options are discussed. This thesis provides a basic foundation for designing an IC of this nature and will give the reader insight into potential areas of further research. At the time of this writing the chip is in fabrication therefore this document does not contain test results.
ContributorsNixon, Cliff (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2013
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
Description
With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.
ContributorsSen, Sourav (Author) / Ayyanar, Raja (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
Description
The demand for cleaner energy technology is increasing very rapidly. Hence it is
important to increase the eciency and reliability of this emerging clean energy technologies.
This thesis focuses on modeling and reliability of solar micro inverters. In
order to make photovoltaics (PV) cost competitive with traditional energy sources,
the economies of scale have been guiding inverter design in two directions: large,
centralized, utility-scale (500 kW) inverters vs. small, modular, module level (300
W) power electronics (MLPE). MLPE, such as microinverters and DC power optimizers,
oer advantages in safety, system operations and maintenance, energy yield,
and component lifetime due to their smaller size, lower power handling requirements,
and module-level power point tracking and monitoring capability [1]. However, they
suer from two main disadvantages: rst, depending on array topology (especially
the proximity to the PV module), they can be subjected to more extreme environments
(i.e. temperature cycling) during the day, resulting in a negative impact to
reliability; second, since solar installations can have tens of thousands to millions of
modules (and as many MLPE units), it may be dicult or impossible to track and
repair units as they go out of service. Therefore identifying the weak links in this
system is of critical importance to develop more reliable micro inverters.
While an overwhelming majority of time and research has focused on PV module
eciency and reliability, these issues have been largely ignored for the balance
of system components. As a relatively nascent industry, the PV power electronics
industry does not have the extensive, standardized reliability design and testing procedures
that exist in the module industry or other more mature power electronics
industries (e.g. automotive). To do so, the critical components which are at risk and
their impact on the system performance has to be studied. This thesis identies and
addresses some of the issues related to reliability of solar micro inverters.
This thesis presents detailed discussions on various components of solar micro inverter
and their design. A micro inverter with very similar electrical specications in
comparison with commercial micro inverter is modeled in detail and veried. Components
in various stages of micro inverter are listed and their typical failure mechanisms
are reviewed. A detailed FMEA is conducted for a typical micro inverter to identify
the weak links of the system. Based on the S, O and D metrics, risk priority number
(RPN) is calculated to list the critical at-risk components. Degradation of DC bus
capacitor is identied as one the failure mechanism and the degradation model is built
to study its eect on the system performance. The system is tested for surge immunity
using standard ring and combinational surge waveforms as per IEEE 62.41 and
IEC 61000-4-5 standards. All the simulation presented in this thesis is performed
using PLECS simulation software.
important to increase the eciency and reliability of this emerging clean energy technologies.
This thesis focuses on modeling and reliability of solar micro inverters. In
order to make photovoltaics (PV) cost competitive with traditional energy sources,
the economies of scale have been guiding inverter design in two directions: large,
centralized, utility-scale (500 kW) inverters vs. small, modular, module level (300
W) power electronics (MLPE). MLPE, such as microinverters and DC power optimizers,
oer advantages in safety, system operations and maintenance, energy yield,
and component lifetime due to their smaller size, lower power handling requirements,
and module-level power point tracking and monitoring capability [1]. However, they
suer from two main disadvantages: rst, depending on array topology (especially
the proximity to the PV module), they can be subjected to more extreme environments
(i.e. temperature cycling) during the day, resulting in a negative impact to
reliability; second, since solar installations can have tens of thousands to millions of
modules (and as many MLPE units), it may be dicult or impossible to track and
repair units as they go out of service. Therefore identifying the weak links in this
system is of critical importance to develop more reliable micro inverters.
While an overwhelming majority of time and research has focused on PV module
eciency and reliability, these issues have been largely ignored for the balance
of system components. As a relatively nascent industry, the PV power electronics
industry does not have the extensive, standardized reliability design and testing procedures
that exist in the module industry or other more mature power electronics
industries (e.g. automotive). To do so, the critical components which are at risk and
their impact on the system performance has to be studied. This thesis identies and
addresses some of the issues related to reliability of solar micro inverters.
This thesis presents detailed discussions on various components of solar micro inverter
and their design. A micro inverter with very similar electrical specications in
comparison with commercial micro inverter is modeled in detail and veried. Components
in various stages of micro inverter are listed and their typical failure mechanisms
are reviewed. A detailed FMEA is conducted for a typical micro inverter to identify
the weak links of the system. Based on the S, O and D metrics, risk priority number
(RPN) is calculated to list the critical at-risk components. Degradation of DC bus
capacitor is identied as one the failure mechanism and the degradation model is built
to study its eect on the system performance. The system is tested for surge immunity
using standard ring and combinational surge waveforms as per IEEE 62.41 and
IEC 61000-4-5 standards. All the simulation presented in this thesis is performed
using PLECS simulation software.
ContributorsManchanahalli Ranganatha, Arkanatha Sastry (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Qin, Jiangchao (Committee member) / Arizona State University (Publisher)
Created2015
Description
The inherent intermittency in solar energy resources poses challenges to scheduling generation, transmission, and distribution systems. Energy storage devices are often used to mitigate variability in renewable asset generation and provide a mechanism to shift renewable power between periods of the day. In the absence of storage, however, time series forecasting techniques can be used to estimate future solar resource availability to improve the accuracy of solar generator scheduling. The knowledge of future solar availability helps scheduling solar generation at high-penetration levels, and assists with the selection and scheduling of spinning reserves. This study employs statistical techniques to improve the accuracy of solar resource forecasts that are in turn used to estimate solar photovoltaic (PV) power generation. The first part of the study involves time series forecasting of the global horizontal irradiation (GHI) in Phoenix, Arizona using Seasonal Autoregressive Integrated Moving Average (SARIMA) models. A comparative study is completed for time series forecasting models developed with different time step resolutions, forecasting start time, forecasting time horizons, training data, and transformations for data measured at Phoenix, Arizona. Approximately 3,000 models were generated and evaluated across the entire study. One major finding is that forecasted values one day ahead are near repeats of the preceding day—due to the 24-hour seasonal differencing—indicating that use of statistical forecasting over multiple days creates a repeating pattern. Logarithmic transform data were found to perform poorly in nearly all cases relative to untransformed or square-root transform data when forecasting out to four days. Forecasts using a logarithmic transform followed a similar profile as the immediate day prior whereas forecasts using untransformed and square-root transform data had smoother daily solar profiles that better represented the average intraday profile. Error values were generally lower during mornings and evenings and higher during midday. Regarding one-day forecasting and shorter forecasting horizons, the logarithmic transformation performed better than untransformed data and square-root transformed data irrespective of forecast horizon for data resolutions of 1-hour, 30-minutes, and 15-minutes.
ContributorsSoundiah Regunathan Rajasekaran, Dhiwaakar Purusothaman (Author) / Johnson, Nathan G (Thesis advisor) / Karady, George G. (Thesis advisor) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2016
Description
The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.
The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
ContributorsKrishnan Achary, Kiran Kumar (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2015