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Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased

Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
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Description
As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC

As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.
ContributorsLuster, Daniel (Author) / Ayyanar, Raja (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2014
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Description
With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies

With the rapid expansion of the photovoltaic industry over the last decade, there has been a huge demand in the PV installations in the residential sector. This thesis focuses on the analysis and implementation of a dc-dc boost converter at photovoltaic sub-module level. The thesis also analyses the various topologies like switched capacitors and extended duty ratio which can be practically implemented in the photovoltaic panels. The results obtained in this work have concentrated on the use of novel strategies to substitute the use of central dc-dc converter used in PV module string connection. The implementation of distributed MPPT at the PV sub-module level is also an integral part of this thesis. Using extensive PLECS simulations, this thesis came to the conclusion that with the design of a proper compensation at the dc interconnection of a series or parallel PV Module Integrated Converter string, the central dc-dc converter can be substituted. The dc-ac interconnection voltage remains regulated at all irradiance level even without a dc-dc central converter at the string end. The foundation work for the hardware implementation has also been carried out. Design of parameters for future hardware implementation has also been presented in detail in this thesis.
ContributorsSen, Sourav (Author) / Ayyanar, Raja (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly

Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
The building sector is one of the main energy consumers within the USA. Energy demand by this sector continues to increase because new buildings are being constructed faster than older ones are retired. Increase in energy demand, in addition to a number of other factors such as the finite nature

The building sector is one of the main energy consumers within the USA. Energy demand by this sector continues to increase because new buildings are being constructed faster than older ones are retired. Increase in energy demand, in addition to a number of other factors such as the finite nature of fossil fuels, population growth, building impact on global climate change, and energy insecurity and independence has led to the increase in awareness towards conservation through the design of energy efficient buildings. Net Zero Energy Building (NZEB), a highly efficient building that produces as much renewable energy as it consumes annually, provides an effective solution to this global concern. The intent of this thesis is to investigate the relationship of an important factor that has a direct impact on NZEB: Floor / Area Ratio (FAR). Investigating this relationship will help to answer a very important question in establishing NZEB in hot-arid climates such as Phoenix, Arizona. The question this thesis presents is: “How big can a building be and still be Net Zero?” When does this concept start to flip and buildings become unable to generate the required renewable energy to achieve energy balance? The investigation process starts with the analysis of a local NZEB, DPR Construction Office, to evaluate the potential increase in building footprint and FAR with respect to the current annual Energy Use Intensity (EUI). Through the detailed analysis of the local NZEB, in addition to the knowledge gained through research, this thesis will offer an FAR calculator tool that can be used by design teams to help assess the net zero potential of their project. The tool analyzes a number of elements within the project such as total building footprint, available surface area for photovoltaic (PV) installation, outdoor circulation and landscape area, parking area and potential parking spots, potential building area in regards to FAR, number of floors based on the building footprint, FAR, required area for photovoltaic installation, photovoltaic system size, and annual energy production, in addition to the maximum potential FAR their project can reach and still be Net Zero.
ContributorsBen Salamah, Fahad (Author) / Bryan, Harvey (Thesis advisor) / Reddy, T. Agami (Committee member) / Ramalingam, Muthukumar (Committee member) / Arizona State University (Publisher)
Created2016
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Description
In this thesis, a digital input class D audio amplifier system which has the ability

to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress

In this thesis, a digital input class D audio amplifier system which has the ability

to reject the power supply noise and nonlinearly of the output stage is presented. The main digital class D feed-forward path is using the fully-digital sigma-delta PWM open loop topology. Feedback loop is used to suppress the power supply noise and harmonic distortions. The design is using global foundry 0.18um technology.

Based on simulation, the power supply rejection at 200Hz is about -49dB with

81dB dynamic range and -70dB THD+N. The full scale output power can reach as high as 27mW and still keep minimum -68dB THD+N. The system efficiency at full scale is about 82%.
ContributorsBai, Jing (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2015
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Description
Schools all around the country are improving the performance of their buildings by adopting high performance design principles. Higher levels of energy efficiency can pave the way for K-12 Schools to achieve net zero energy (NZE) conditions, a state where the energy generated by on-site renewable sources are sufficient to

Schools all around the country are improving the performance of their buildings by adopting high performance design principles. Higher levels of energy efficiency can pave the way for K-12 Schools to achieve net zero energy (NZE) conditions, a state where the energy generated by on-site renewable sources are sufficient to meet the cumulative annual energy demands of the facility. A key capability for the proliferation of Net Zero Energy Buildings (NZEB) is the need for a design methodology that identifies the optimum mix of energy efficient design features to be incorporated into the building. The design methodology should take into account the interaction effects of various energy efficiency measures as well as their associated costs so that life cycle cost can be minimized for the entire life span of the building.

This research aims at developing such a methodology for generating cost effective net zero energy solutions for school buildings. The Department of Energy (DOE) prototype primary school, meant to serve as the starting baseline, was modeled in the building energy simulation software eQUEST and made compliant with the requirement of ASHRAE 90.1-2007. Commonly used efficiency measures, for which credible initial cost and maintenance data were available, were selected as the parametric design set. An initial sensitivity analysis was conducted by using the Morris Method to rank the efficiency measures in terms of their importance and interaction strengths. A sequential search technique was adopted to search the solution space and identify combinations that lie near the Pareto-optimal front; this allowed various minimum cost design solutions to be identified corresponding to different energy savings levels.

Based on the results of this study, it was found that the cost optimal combination of measures over the 30 year analysis span resulted in an annual energy cost reduction of 47%, while net zero site energy conditions were achieved by the addition of a 435 kW photovoltaic generation system that covered 73% of the roof area. The simple payback period for the additional technology required to achieve NZE conditions was calculated to be 26.3 years and carried a 37.4% premium over the initial building construction cost. The study identifies future work in how to automate this computationally conservative search technique so that it can provide practical feedback to the building designer during all stages of the design process.
ContributorsIslam, Mohammad Moshfiqul (Author) / Reddy, T. Agami (Thesis advisor) / Bryan, Harvey J. (Committee member) / Addison, Marlin (Committee member) / Arizona State University (Publisher)
Created2016
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Description
The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with

The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.

This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.

The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.
ContributorsKrishnan Achary, Kiran Kumar (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2015