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Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as

Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased

Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has

The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static (QS) description of the MOSFET. The model is implemented in two widely used circuit simulators and tested for speed and convergence. It is verified by comparison with technology computer aided design (TCAD) simulations and experimental data, and by application of a recently developed benchmark test for NQS MOSFET models. In addition, a new and simple technique to characterize NQS and gate resistance, Rgate, MOS model parameters from measured data has been presented. In the process of experimental model verification, the effects of bulk resistance on MOSFET characteristics is investigated both theoretically and experimentally to separate it from the NQS effects.
ContributorsZhu, Zeqin (Author) / Gildenblat, Gennady (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Barnaby, Hugh (Committee member) / Mcandrew, Colin C (Committee member) / Arizona State University (Publisher)
Created2012
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Description
In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB)

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.
ContributorsKim, Kibeom (Author) / Ozev, Sule (Thesis advisor) / Kitchen, Jennifer (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2013
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Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This

With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
ContributorsBikkina, Phaneendra Kumar (Author) / Barnaby, Hugh (Thesis advisor) / Mikkola, Esko (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of

The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of such circuits. In order to develop wide temperature range compact models, fourteen different geometries of n-channel and p-channel MOSFETs manufactured in a 0.18μm mixed-signal process were electrically characterized over a temperature range of 40 K to 298 K. Electrical characterization included ID-VG and ID-VD under different drain, body and gate biases respectively. The effects of low-temperature operation on the performance of 0.18μm MOSFETs have been studied and discussed in terms of sub-threshold characteristics, threshold voltage, the effect of the body bias and linearity of the device. As it is well understood, the subthreshold slope, the threshold voltage, drive currents of the MOSFETs increase when the temperature of the MOSFETs is lowered, which makes it advantageous to operate the MOSFETs at low-temperatures. However the internal linearity gm1/gm3 of the MOSFETs degrades as the temperature of the MOSFETs is lowered, and the performance of the MOSFETs can be affected by the interface traps that exist in higher density close to conduction band and valence band energy levels, as the Fermi-level moves closer to bandgap edges when MOSFETs are operated at cryogenic temperatures.
ContributorsKathuria, Achal (Author) / Barnaby, Hugh (Thesis advisor) / Schroder, Dieter K. (Committee member) / Vermeire, Bert (Committee member) / Arizona State University (Publisher)
Created2010
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Description
ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR

ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator.
ContributorsSwaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012