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This is a test plan document for Team Aegis' capstone project that has the goal of mitigating single event upsets in NAND flash memory caused by space radiation.

ContributorsForman, Oliver Ethan (Co-author) / Smith, Aiden (Co-author) / Salls, Demetra (Co-author) / Kozicki, Michael (Thesis director) / Hodge, Chris (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
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Description

Radiation hardening of electronic devices is generally necessary when designing for the space environment. Non-volatile memory technologies are of particular concern when designing for the mitigation of radiation effects. Among other radiation effects, single-event upsets can create bit flips in non-volatile memories, leading to data corruption. In this paper, a

Radiation hardening of electronic devices is generally necessary when designing for the space environment. Non-volatile memory technologies are of particular concern when designing for the mitigation of radiation effects. Among other radiation effects, single-event upsets can create bit flips in non-volatile memories, leading to data corruption. In this paper, a Verilog implementation of a Reed-Solomon error-correcting code is considered for its ability to mitigate the effects of single-event upsets on non-volatile memories. This implementation is compared with the simpler procedure of using triple modular redundancy.

ContributorsSmith, Aidan W (Author) / Kozicki, Michael (Thesis director) / Hodge, Chris (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05