Matching Items (2)
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Description
Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency

Error correcting systems have put increasing demands on system designers, both due to increasing error correcting requirements and higher throughput targets. These requirements have led to greater silicon area, power consumption and have forced system designers to make trade-offs in Error Correcting Code (ECC) functionality. Solutions to increase the efficiency of ECC systems are very important to system designers and have become a heavily researched area.

Many such systems incorporate the Bose-Chaudhuri-Hocquenghem (BCH) method of error correcting in a multi-channel configuration. BCH is a commonly used code because of its configurability, low storage overhead, and low decoding requirements when compared to other codes. Multi-channel configurations are popular with system designers because they offer a straightforward way to increase bandwidth. The ECC hardware is duplicated for each channel and the throughput increases linearly with the number of channels. The combination of these two technologies provides a configurable and high throughput ECC architecture.

This research proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. In this thesis, I examine how error frequency effects the utilization of BCH hardware. Rather than implement each decoder as a single pipeline of independent decoding stages, the channels are considered together and served by a pool of decoding stages. Modified hardware blocks for handling common cases are included and the pool is sized based on an acceptable, but negligible decrease in performance.
ContributorsDill, Russell (Author) / Shrivastava, Aviral (Thesis advisor) / Oh, Hyunok (Committee member) / Sen, Arunabha (Committee member) / Arizona State University (Publisher)
Created2015
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Description

Radiation hardening of electronic devices is generally necessary when designing for the space environment. Non-volatile memory technologies are of particular concern when designing for the mitigation of radiation effects. Among other radiation effects, single-event upsets can create bit flips in non-volatile memories, leading to data corruption. In this paper, a

Radiation hardening of electronic devices is generally necessary when designing for the space environment. Non-volatile memory technologies are of particular concern when designing for the mitigation of radiation effects. Among other radiation effects, single-event upsets can create bit flips in non-volatile memories, leading to data corruption. In this paper, a Verilog implementation of a Reed-Solomon error-correcting code is considered for its ability to mitigate the effects of single-event upsets on non-volatile memories. This implementation is compared with the simpler procedure of using triple modular redundancy.

ContributorsSmith, Aidan W (Author) / Kozicki, Michael (Thesis director) / Hodge, Chris (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05