Filtering by
- All Subjects: Frequency Selective Surfaces
- All Subjects: Single Event Transient (SET)
- Creators: Allee, David
- Creators: Chakraborty, Partha
- Creators: Sisk, Ryan Derek
This work begins by exploring the different radiation hardened flip-flops that have been proposed in the literature and classifies them based on the different hardening techniques.
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient tolerance is demonstrated by simulations using it in a radiation hardened by design master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element is used in the implementation of an 8-bit, 8051 designed in the TSMC 130 nm bulk CMOS.
A single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate in most modern scaled process technologies. The design of flip-flops is made more difficult with increasing multi-node charge collection, which requires that charge storage and other sensitive nodes be separated so that one impinging radiation particle does not affect redundant nodes simultaneously. We describe a correct-by-construction design methodology to determine a-priori which hardened FF nodes must be separated, as well as a general interleaving scheme to achieve this separation. We apply the methodology to radiation hardened flip-flops and demonstrate optimal circuit physical organization for protection against multi-node charge collection.
Finally, the methodology is utilized to provide critical node separation for a new hardened flip-flop design that reduces the power and area by 31% and 35% respectively compared to a temporal FF with similar hardness. The hardness is verified and compared to other published designs via the proposed systematic simulation approach that comprehends multiple node charge collection and tests resiliency to upsets at all internal and input nodes. Comparison of the hardness, as measured by estimated upset cross-section, is made to other published designs. Additionally, the importance of specific circuit design aspects to achieving hardness is shown.
This thesis details the design process of a variable gain amplifier (VGA) based circuit which maintains a consistent output power over a wide range of input power signals. This effect is achieved by using power detection circuitry to adjust the gain of the VGA based on the current input power so that it is amplifier to a set power level. The paper details the theory behind this solutions as well as the design process which includes both simulations and physical testing of the actual circuit. It also analyses results of these tests and gives suggestions as to what could be done to further improve the design. The VGA based constant output power solution was designed as a section of a larger circuit which was developed as part of a senior capstone project, which is also briefly described in the paper.
The honors thesis presented in this document describes an extension to an electrical engineering capstone project whose scope is to develop the receiver electronics for an RF interrogator. The RF interrogator functions by detecting the change in resonant frequency of (i.e, frequency of maximum backscatter from) a target resulting from an environmental input. The general idea of this honors project was to design three frequency selective surfaces that would act as surrogate backscattering or reflecting targets that each contains a distinct frequency response. Using 3-D electromagnetic simulation software, three surrogate targets exhibiting bandpass frequency responses at distinct frequencies were designed and presented in this thesis.