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- All Subjects: Chamber music
Description
In order to cope with the decreasing availability of symphony jobs and collegiate faculty positions, many musicians are starting to pursue less traditional career paths. Also, to combat declining audiences, musicians are exploring ways to cultivate new and enthusiastic listeners through relevant and engaging performances. Due to these challenges, many community-based chamber music ensembles have been formed throughout the United States. These groups not only focus on performing classical music, but serve the needs of their communities as well. The problem, however, is that many musicians have not learned the business skills necessary to create these career opportunities. In this document I discuss the steps ensembles must take to develop sustainable careers. I first analyze how groups build a strong foundation through getting to know their communities and creating core values. I then discuss branding and marketing so ensembles can develop a public image and learn how to publicize themselves. This is followed by an investigation of how ensembles make and organize their money. I then examine the ways groups ensure long-lasting relationships with their communities and within the ensemble. I end by presenting three case studies of professional ensembles to show how groups create and maintain successful careers. Ensembles must develop entrepreneurship skills in addition to cultivating their artistry. These business concepts are crucial to the longevity of chamber groups. Through interviews of successful ensemble members and my own personal experiences in the Tetra String Quartet, I provide a guide for musicians to use when creating a community-based ensemble.
ContributorsDalbey, Jenna (Author) / Landschoot, Thomas (Thesis advisor) / McLin, Katherine (Committee member) / Ryan, Russell (Committee member) / Solis, Theodore (Committee member) / Spring, Robert (Committee member) / Arizona State University (Publisher)
Created2013
Description
American Primitive is a composition written for wind ensemble with an instrumentation of flute, oboe, clarinet, bass clarinet, alto, tenor, and baritone saxophones, trumpet, horn, trombone, euphonium, tuba, piano, and percussion. The piece is approximately twelve minutes in duration and was written September - December 2013. American Primitive is absolute music (i.e. it does not follow a specific narrative) comprising blocks of distinct, contrasting gestures which bookend a central region of delicate textural layering and minimal gestural contrast. Though three gestures (a descending interval followed by a smaller ascending interval, a dynamic swell, and a chordal "chop") were consciously employed throughout, it is the first gesture of the three that creates a sense of unification and overall coherence to the work. Additionally, the work challenges listeners' expectations of traditional wind ensemble music by featuring the trumpet as a quasi-soloist whose material is predominately inspired by transcriptions of jazz solos. This jazz-inspired material is at times mimicked and further developed by the ensemble, also often in a soloistic manner while the trumpet maintains its role throughout. This interplay of dialogue between the "soloists" and the "ensemble" further skews listeners' conceptions of traditional wind ensemble music by featuring almost every instrument in the ensemble. Though the term "American Primitive" is usually associated with the "naïve art" movement, it bears no association to the music presented in this work. Instead, the term refers to the author's own compositional attitudes, education, and aesthetic interests.
ContributorsJandreau, Joshua (Composer) / Rockmaker, Jody D (Thesis advisor) / Rogers, Rodney I (Committee member) / Demars, James R (Committee member) / Arizona State University (Publisher)
Created2014
Description
This project is a practical annotated bibliography of original works for oboe trio with the specific instrumentation of two oboes and English horn. Presenting descriptions of 116 readily available oboe trios, this project is intended to promote awareness, accessibility, and performance of compositions within this genre.
The annotated bibliography focuses exclusively on original, published works for two oboes and English horn. Unpublished works, arrangements, works that are out of print and not available through interlibrary loan, or works that feature slightly altered instrumentation are not included.
Entries in this annotated bibliography are listed alphabetically by the last name of the composer. Each entry includes the dates of the composer and a brief biography, followed by the title of the work, composition date, commission, and dedication of the piece. Also included are the names of publishers, the length of the entire piece in minutes and seconds, and an incipit of the first one to eight measures for each movement of the work.
In addition to providing a comprehensive and detailed bibliography of oboe trios, this document traces the history of the oboe trio and includes biographical sketches of each composer cited, allowing readers to place the genre of oboe trios and each individual composition into its historical context. Four appendices at the end include a list of trios arranged alphabetically by composer's last name, chronologically by the date of composition, and by country of origin and a list of publications of Ludwig van Beethoven's oboe trios from the 1940s and earlier.
The annotated bibliography focuses exclusively on original, published works for two oboes and English horn. Unpublished works, arrangements, works that are out of print and not available through interlibrary loan, or works that feature slightly altered instrumentation are not included.
Entries in this annotated bibliography are listed alphabetically by the last name of the composer. Each entry includes the dates of the composer and a brief biography, followed by the title of the work, composition date, commission, and dedication of the piece. Also included are the names of publishers, the length of the entire piece in minutes and seconds, and an incipit of the first one to eight measures for each movement of the work.
In addition to providing a comprehensive and detailed bibliography of oboe trios, this document traces the history of the oboe trio and includes biographical sketches of each composer cited, allowing readers to place the genre of oboe trios and each individual composition into its historical context. Four appendices at the end include a list of trios arranged alphabetically by composer's last name, chronologically by the date of composition, and by country of origin and a list of publications of Ludwig van Beethoven's oboe trios from the 1940s and earlier.
ContributorsSassaman, Melissa Ann (Author) / Schuring, Martin (Thesis advisor) / Buck, Elizabeth (Committee member) / Holbrook, Amy (Committee member) / Hill, Gary (Committee member) / Arizona State University (Publisher)
Created2014
Description
As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but they become difficult to program. Some existing architectures provide a middle ground by providing some shared memory in the hardware. Specifically, the 48-core Intel Single-chip Cloud Computer (SCC) provides some off-chip (DRAM) shared memory some on-chip (SRAM) shared memory. We call such architectures Hybrid Shared Memory, or HSM, manycore architectures. However, how to efficiently execute multi-threaded programs on HSM architectures is an open problem. To be able to execute a multi-threaded program correctly on HSM architectures, the compiler must: i) identify all the shared data and map it to the shared memory, and ii) map the frequently accessed shared data to the on-chip shared memory. This work presents a source-to-source translator written using CETUS that identifies a conservative superset of all the shared data in a multi-threaded application and maps it to the shared memory such that it enables execution on HSM architectures.
ContributorsRawat, Tushar (Author) / Shrivastava, Aviral (Thesis advisor) / Dasgupta, Partha (Committee member) / Fainekos, Georgios (Committee member) / Arizona State University (Publisher)
Created2014
Description
In recent years, we have observed the prevalence of stream applications in many embedded domains. Stream programs distinguish themselves from traditional sequential programming languages through well defined independent actors, explicit data communication, and stable code/data access patterns. In order to achieve high performance and low power, scratch pad memory (SPM) has been introduced in today's embedded multicore processors. Current design frameworks for developing stream applications on SPM enhanced embedded architectures typically do not include a compiler that can perform automatic partitioning, mapping and scheduling under limited on-chip SPM capacities and memory access delays. Consequently, many designs are implemented manually, which leads to lengthy tasks and inferior designs. In this work, optimization techniques that automatically compile stream programs onto embedded multi-core architectures are proposed. As an initial case study, we implemented an automatic target recognition (ATR) algorithm on the IBM Cell Broadband Engine (BE). Then integer linear programming (ILP) and heuristic approaches were proposed to schedule stream programs on a single core embedded processor that has an SPM with code overlay. Later, ILP and heuristic approaches for Compiling Stream programs on SPM enhanced Multicore Processors (CSMP) were studied. The proposed CSMP ILP and heuristic approaches do not optimize for cycles in stream applications. Further, the number of software pipeline stages in the implementation is dependent on actor to processing engine (PE) mapping and is uncontrollable. We next presented a Retiming technique for Throughput optimization on Embedded Multi-core processors (RTEM). RTEM approach inherently handles cycles and can accept an upper bound on the number of software pipeline stages to be generated. We further enhanced RTEM by incorporating unrolling (URSTEM) that preserves all the beneficial properties of RTEM heuristic and also scales with the number of PEs through unrolling.
ContributorsChe, Weijia (Author) / Chatha, Karam Singh (Thesis advisor) / Vrudhula, Sarma (Committee member) / Chakrabarti, Chaitali (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2012
ContributorsPagano, Caio, 1940- (Performer) / Mechetti, Fabio (Conductor) / Buck, Elizabeth (Performer) / Schuring, Martin (Performer) / Spring, Robert (Performer) / Rodrigues, Christiano (Performer) / Landschoot, Thomas (Performer) / Rotaru, Catalin (Performer) / Avanti Festival Orchestra (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-02
Description
Caches have long been used to reduce memory access latency. However, the increased complexity of cache coherence brings significant challenges in processor design as the number of cores increases. While making caches scalable is still an important research problem, some researchers are exploring the possibility of a more power-efficient SRAM called scratchpad memories or SPMs. SPMs consume significantly less area, and are more energy-efficient per access than caches, and therefore make the design of on-chip memories much simpler. Unlike caches, which fetch data from memories automatically, an SPM requires explicit instructions for data transfers. SPM-only architectures are thus named as software managed manycore (SMM), since the data movements of such architectures rely on software. SMM processors have been widely used in different areas, such as embedded computing, network processing, or even high performance computing. While SMM processors provide a low-power platform, the hardware alone does not guarantee power efficiency, if applications on such processors deliver low performance. Efficient software techniques are therefore required. A big body of management techniques for SMM architectures are compiler-directed, as inserting data movement operations by hand forces programmers to trace flow of data, which can be error-prone and sometimes difficult if not impossible. This thesis develops compiler-directed techniques to manage data transfers for embedded applications on SMMs efficiently. The techniques analyze and find out the proper program points and insert data movement instructions accordingly. The techniques manage code, stack and heap data of applications, and reduce execution time by 14%, 52% and 80% respectively compared to their predecessors on typical embedded applications. On top of managing local data, a technique is also developed for shared data in SMM architectures. Experimental results show it achieves more than 2X speedup than the previous technique on average.
ContributorsCai, Jian (Author) / Shrivastava, Aviral (Thesis advisor) / Wu, Carole (Committee member) / Ren, Fengbo (Committee member) / Dasgupta, Partha (Committee member) / Arizona State University (Publisher)
Created2017
Description
With the end of Dennard scaling and Moore's law, architects have moved towards
heterogeneous designs consisting of specialized cores to achieve higher performance
and energy efficiency for a target application domain. Applications of linear algebra
are ubiquitous in the field of scientific computing, machine learning, statistics,
etc. with matrix computations being fundamental to these linear algebra based solutions.
Design of multiple dense (or sparse) matrix computation routines on the
same platform is quite challenging. Added to the complexity is the fact that dense
and sparse matrix computations have large differences in their storage and access
patterns and are difficult to optimize on the same architecture. This thesis addresses
this challenge and introduces a reconfigurable accelerator that supports both dense
and sparse matrix computations efficiently.
The reconfigurable architecture has been optimized to execute the following linear
algebra routines: GEMV (Dense General Matrix Vector Multiplication), GEMM
(Dense General Matrix Matrix Multiplication), TRSM (Triangular Matrix Solver),
LU Decomposition, Matrix Inverse, SpMV (Sparse Matrix Vector Multiplication),
SpMM (Sparse Matrix Matrix Multiplication). It is a multicore architecture where
each core consists of a 2D array of processing elements (PE).
The 2D array of PEs is of size 4x4 and is scheduled to perform 4x4 sized matrix
updates efficiently. A sequence of such updates is used to solve a larger problem inside
a core. A novel partitioned block compressed sparse data structure (PBCSC/PBCSR)
is used to perform sparse kernel updates. Scalable partitioning and mapping schemes
are presented that map input matrices of any given size to the multicore architecture.
Design trade-offs related to the PE array dimension, size of local memory inside a core
and the bandwidth between on-chip memories and the cores have been presented. An
optimal core configuration is developed from this analysis. Synthesis results using a 7nm PDK show that the proposed accelerator can achieve a performance of upto
32 GOPS using a single core.
heterogeneous designs consisting of specialized cores to achieve higher performance
and energy efficiency for a target application domain. Applications of linear algebra
are ubiquitous in the field of scientific computing, machine learning, statistics,
etc. with matrix computations being fundamental to these linear algebra based solutions.
Design of multiple dense (or sparse) matrix computation routines on the
same platform is quite challenging. Added to the complexity is the fact that dense
and sparse matrix computations have large differences in their storage and access
patterns and are difficult to optimize on the same architecture. This thesis addresses
this challenge and introduces a reconfigurable accelerator that supports both dense
and sparse matrix computations efficiently.
The reconfigurable architecture has been optimized to execute the following linear
algebra routines: GEMV (Dense General Matrix Vector Multiplication), GEMM
(Dense General Matrix Matrix Multiplication), TRSM (Triangular Matrix Solver),
LU Decomposition, Matrix Inverse, SpMV (Sparse Matrix Vector Multiplication),
SpMM (Sparse Matrix Matrix Multiplication). It is a multicore architecture where
each core consists of a 2D array of processing elements (PE).
The 2D array of PEs is of size 4x4 and is scheduled to perform 4x4 sized matrix
updates efficiently. A sequence of such updates is used to solve a larger problem inside
a core. A novel partitioned block compressed sparse data structure (PBCSC/PBCSR)
is used to perform sparse kernel updates. Scalable partitioning and mapping schemes
are presented that map input matrices of any given size to the multicore architecture.
Design trade-offs related to the PE array dimension, size of local memory inside a core
and the bandwidth between on-chip memories and the cores have been presented. An
optimal core configuration is developed from this analysis. Synthesis results using a 7nm PDK show that the proposed accelerator can achieve a performance of upto
32 GOPS using a single core.
ContributorsAnimesh, Saurabh (Author) / Chakrabarti, Chaitali (Thesis advisor) / Brunhaver, John (Committee member) / Ren, Fengbo (Committee member) / Arizona State University (Publisher)
Created2018
ContributorsSchuring, Martin (Performer) / Stromberg, Eric (Performer) / Campbell, Andrew (Pianist) (Performer) / ASU Library. Music Library (Publisher)
Created2018-08-19
ContributorsDe La Cruz, Nathaniel (Performer) / LoGiudice, Rosa (Contributor) / Tallino, Michael (Performer) / McKinch, Riley (Performer) / Li, Yuhui (Performer) / Armenta, Tyler (Contributor) / Gonzalez, David (Performer) / Jones, Tarin (Performer) / Ryall, Blake (Performer) / Senseman, Stephen (Performer)
Created2018-10-10