Matching Items (3)

Filtering by

Clear all filters

149370-Thumbnail Image.png

Self resonant third harmonic mixer for 60 GHz transmitter

Description

ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer

ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.

Contributors

Agent

Created

Date Created
2010

151252-Thumbnail Image.png

Triple sampling an application to a 14b 10 MS/s cyclic converter

Description

Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges

Semiconductor device scaling has kept up with Moore's law for the past decades and they have been scaling by a factor of half every one and half years. Every new generation of device technology opens up new opportunities and challenges and especially so for analog design. High speed and low gain is characteristic of these processes and hence a tradeoff that can enable to get back gain by trading speed is crucial. This thesis proposes a solution that increases the speed of sampling of a circuit by a factor of three while reducing the specifications on analog blocks and keeping the power nearly constant. The techniques are based on the switched capacitor technique called Correlated Level Shifting. A triple channel Cyclic ADC has been implemented, with each channel working at a sampling frequency of 3.33MS/s and a resolution of 14 bits. The specifications are compared with that based on a traditional architecture to show the superiority of the proposed technique.

Contributors

Agent

Created

Date Created
2012

157839-Thumbnail Image.png

Multiscale Modeling of Thermal and Electrical Characteristics in Silicon CMOS Devices

Description

This dissertation explores thermal effects and electrical characteristics in metal-oxide-semiconductor field effect transistor (MOSFET) devices and circuits using a multiscale dual-carrier approach. Simulating electron and hole transport with carrier-phonon interactions for thermal transport allows for the study of complementary logic

This dissertation explores thermal effects and electrical characteristics in metal-oxide-semiconductor field effect transistor (MOSFET) devices and circuits using a multiscale dual-carrier approach. Simulating electron and hole transport with carrier-phonon interactions for thermal transport allows for the study of complementary logic circuits with device level accuracy in electrical characteristics and thermal effects. The electrical model is comprised of an ensemble Monte Carlo solution to the Boltzmann Transport Equation coupled with an iterative solution to two-dimensional (2D) Poisson’s equation. The thermal model solves the energy balance equations accounting for carrier-phonon and phonon-phonon interactions. Modeling of circuit behavior uses parametric iteration to ensure current and voltage continuity. This allows for modeling of device behavior, analyzing circuit performance, and understanding thermal effects.

The coupled electro-thermal approach, initially developed for individual n-channel MOSFET (NMOS) devices, now allows multiple devices in tandem providing a platform for better comparison with heater-sensor experiments. The latest electro-thermal solver allows simulation of multiple NMOS and p-channel MOSFET (PMOS) devices, providing a platform for the study of complementary MOSFET (CMOS) circuit behavior. Modeling PMOS devices necessitates the inclusion of hole transport and hole-phonon interactions. The analysis of CMOS circuits uses the electro-thermal device simulation methodology alongside parametric iteration to ensure current continuity. Simulating a CMOS inverter and analyzing the extracted voltage transfer characteristics verifies the efficacy of this methodology. This work demonstrates the effectiveness of the dual-carrier electro-thermal solver in simulating thermal effects in CMOS circuits.

Contributors

Agent

Created

Date Created
2019