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- All Subjects: Infrared
- All Subjects: NASA JPL
- All Subjects: ROIC
- Creators: Carpenter, Ray
- Status: Published
Description
HgCdTe is the dominant material currently in use for infrared (IR) focal-plane-array (FPA) technology. In this dissertation, transmission electron microscopy (TEM) was used for the characterization of epitaxial HgCdTe epilayers and HgCdTe-based devices. The microstructure of CdTe surface passivation layers deposited either by hot-wall epitaxy (HWE) or molecular beam epitaxy (MBE) on HgCdTe heterostructures was evaluated. The as-deposited CdTe passivation layers were polycrystalline and columnar. The CdTe grains were larger and more irregular when deposited by HWE, whereas those deposited by MBE were generally well-textured with mostly vertical grain boundaries. Observations and measurements using several TEM techniques showed that the CdTe/HgCdTe interface became considerably more abrupt after annealing, and the crystallinity of the CdTe layer was also improved. The microstructure and compositional profiles of CdTe(211)B/ZnTe/Si(211) heterostructures grown by MBE was investigated. Many inclined {111}-type stacking faults were present throughout the thin ZnTe layer, terminating near the point of initiation of CdTe growth. A rotation angle of about 3.5° was observed between lattice planes of the Si substrate and the final CdTe epilayer. Lattice parameter measurement and elemental profiles indicated that some local intermixing of Zn and Cd had taken place. The average widths of the ZnTe layer and the (Cd, Zn)Te transition region were found to be roughly 6.5 nm and 3.5 nm, respectively. Initial observations of CdTe(211)B/GaAs(211) heterostructures indicated much reduced defect densities near the vicinity of the substrate and within the CdTe epilayers. HgCdTe epilayers grown on CdTe(211)B/GaAs(211) composite substrate were generally of high quality, despite the presence of precipitates at the HgCdTe/CdTe interface. The microstructure of HgCdSe thin films grown by MBE on ZnTe/Si(112) and GaSb(112) substrates were investigated. The quality of the HgCdSe growth was dependent on the growth temperature and materials flux, independent of the substrate. The materials grown at 100°C were generally of high quality, while those grown at 140°C had {111}-type stacking defects and high dislocation densities. For epitaxial growth of HgCdSe on GaSb substrates, better preparation of the GaSb buffer layer will be essential in order to ensure that high-quality HgCdSe can be grown.
ContributorsZhao, Wenfeng (Author) / Smith, David J. (Thesis advisor) / McCartney, Martha (Committee member) / Carpenter, Ray (Committee member) / Bennett, Peter (Committee member) / Treacy, Michael J. (Committee member) / Arizona State University (Publisher)
Created2011
Description
Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ContributorsPraveen, Subramanya Chilukuri (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019