Matching Items (7)
Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
Description
The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an extremely cost effective way. Higher integration leads to electronics with increased functionality and a smaller finished product. The MESFETs are designed in-house by the research group led by Dr. Trevor Thornton. The layouts are then sent to multi-project wafer (MPW) integrated circuit foundry companies, such as the Metal Oxide Semiconductor Implementation Service (MOSIS) to be fabricated. Once returned, the electrical characteristics of the devices are measured. The MESFET has been implemented in various applications by the research group, including the low dropout linear regulator (LDO) and RF power amplifier. An advantage of the MESFET is that it can function in extreme environments such as space, allowing for complex electrical systems to continue functioning properly where traditional transistors would fail.
ContributorsKam, Jason (Author) / Thornton, Trevor (Thesis director) / Goryll, Michael (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2015-05
Description
In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.
ContributorsSoligo, Riccardo (Author) / Saraniti, Marco (Thesis advisor) / Goodnick, Stephen M (Committee member) / Chowdhury, Srabanti (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2016
Description
NGExtract 2 is a complete transistor (MOSFET) parameter extraction solution based upon the original computer program NGExtract by Rahul Shringarpure written in February 2007. NGExtract 2 is written in Java and based around the circuit simulator NGSpice. The goal of the program is to be used to produce accurate transistor models based around real-world transistor data. The program contains numerous improvements to the original program:
• Completely rewritten with performance and usability in mind
• Cross-Platform vs. Linux Only
• Simple installation procedure vs. compilation and manual library configuration
• Self-contained, single file runtime
• Particle Swarm Optimization routine
NGExtract 2 works by plotting the Ids vs. Vds and Ids vs. Vgs curves of a simulation model and the measured, real-world data. The user can adjust model parameters and re-simulate to attempt to match the curves. The included Particle Swarm Optimization routine attempts to automate this process by iteratively attempting to improve a solution by measuring its sum-squared error against the real-world data that the user has provided.
• Completely rewritten with performance and usability in mind
• Cross-Platform vs. Linux Only
• Simple installation procedure vs. compilation and manual library configuration
• Self-contained, single file runtime
• Particle Swarm Optimization routine
NGExtract 2 works by plotting the Ids vs. Vds and Ids vs. Vgs curves of a simulation model and the measured, real-world data. The user can adjust model parameters and re-simulate to attempt to match the curves. The included Particle Swarm Optimization routine attempts to automate this process by iteratively attempting to improve a solution by measuring its sum-squared error against the real-world data that the user has provided.
ContributorsVetrano, Michael Thomas (Author) / Allee, David (Thesis director) / Gorur, Ravi (Committee member) / Bakkaloglu, Bertan (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor)
Created2013-05
Description
Diamond transistors are promising as high-power and high-frequency devices having higher efficiencies than conventional transistors. Diamond possesses superior electronic properties, such as a high bandgap (5.47 eV), high breakdown voltage (>10 MV cm−1 ), high electron and hole mobilities [4500 and 3800 cm2 V−1 · s−1, respectively], high electron and hole saturation velocities (1.5 × 107 and 1.05 × 107 cm s−1, respectively), and high thermal conductivity [22 W cm−1 · K−1], compared to conventional semiconductors. Reportedly, the diamond field-effect transistors (FETs) have shown transition frequencies (fT) of 45 and 70 GHz, maximum oscillation frequency (fmax) of 120 GHz, and radiofrequency (RF) power densities of 2.1 and 3.8 W mm−1 at 1 GHz. A two-dimensional-hole-gas (2DHG) surface channel forms on H-diamond by transfer doping from adsorbates/dielectrics in contact with H-diamond surface. However, prior studies indicate that charge transfer at the dielectric/ H-diamond interface could result in relatively low mobility attributed to interface scattering from the transferred negative charge to acceptor region. H-terminated diamond exhibits a negative electron affinity (NEA) of -1.1 to -1.3 eV, which is crucial to enable charge transfer doping. To overcome these limitations modulation doping, that is, selective doping, that leads to spatial separation of the MoO3 acceptor layer from the hole channel on H-diamond has been proposed. Molybdenum oxide (MoO3) was used as dielectric as it has electron affinity of 5.9eV and could align its conduction band minimum (CBM) below the valence band maximum (VBM) of H-terminated diamond. The band alignment provides the driving potential for charge transfer. Hafnium oxide (HfO2) was used as interfacial layer since it is a high-k oxide insulator (∼25), having large Eg (5.6 eV), high critical breakdown field, and high thermal stability. This study presents photoemission measurements of the electronic band alignments of the MoO3/HfO2/H-diamond layer structure to gain insight into the driving potential for the negative charge transfer and the location of the negative charges near the interface, in the HfO2 layer or in the MoO3 layer. The diamond hole concentration, mobility, and sheet resistance were characterized for MoO3/HfO2/H-Diamond with HfO2 layers of 0, 2 and 4 nm thickness.
ContributorsDeshmukh, Aditya Vilasrao (Author) / Nemanich, Robert J. (Thesis advisor) / Alford, Terry (Committee member) / Yang, Sui (Committee member) / Arizona State University (Publisher)
Created2024
Description
This thesis project explores the TID susceptibility of 12nm FinFETs. Along with the basic effects, the mechanisms and patterns of these effects are analyzed and reported.
ContributorsWallace, Trace (Author) / Barnaby, Hugh (Thesis director) / Marinella, Mathew (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / Dean, W.P. Carey School of Business (Contributor)
Created2022-05