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Description
The advent of threshold logic simplifies the traditional Boolean logic to the single level multi-input function. Threshold logic latch (TLL), among implementations of threshold logic, is functionally equivalent to a multi-input function with an edge triggered flip-flop, which stands out to improve area and both dynamic and leakage power consumption,

The advent of threshold logic simplifies the traditional Boolean logic to the single level multi-input function. Threshold logic latch (TLL), among implementations of threshold logic, is functionally equivalent to a multi-input function with an edge triggered flip-flop, which stands out to improve area and both dynamic and leakage power consumption, providing an appropriate design alternative. Accordingly, the TLL standard cell library is designed. Through technology mapping, hybrid circuit is generated by absorbing the logic cone backward from each flip-flip to get the smallest remaining feeder. With the scan test methodology adopted, design for testability (DFT) is proposed, including scan element design and scan chain insertion. Test synthesis flow is then introduced, according to the Cadence tool, RTL compiler. Test application is the process of applying vectors and the response analysis, which is mainly about the testbench design. A parameterized generic self-checking Verilog testbench is designed for static fault detection. Test development refers to the fault modeling, and test generation. Firstly, functional truth table test generation on TLL cells is proposed. Before the truth table test of the threshold function, the dependence of sequence of vectors applied, i.e., the dependence of current state on the previous state, should be eliminated. Transition test (dynamic pattern) on all weak inputs is proved to be able to test the reset function, which is supposed to erase the history in the reset phase before every evaluation phase. Remaining vectors in the truth table except the weak inputs are then applied statically (static pattern). Secondly, dynamic patterns for all weak inputs are proposed to detect structural transistor level faults analyzed in the TLL cell, with single fault assumption and stuck-at faults, stuck-on faults, and stuck-open faults under consideration. Containing those patterns, the functional test covers all testable structural faults inside the TLL. Thirdly, with the scope of the whole hybrid netlist, the procedure of test generation is proposed with three steps: scan chain test; test of feeders and other scan elements except TLLs; functional pattern test of TLL cells. Implementation of this procedure is discussed in the automatic test pattern generation (ATPG) chapter.
ContributorsHu, Yang (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Soft magnetic materials have been studied extensively in the recent past due to their applications in micro-transformers, micro-inductors, spin dependent memories etc. The unique features of these materials are the high frequency operability and high magnetic anisotropy. High uniaxial anisotropy is one of the most important properties for these materials.

Soft magnetic materials have been studied extensively in the recent past due to their applications in micro-transformers, micro-inductors, spin dependent memories etc. The unique features of these materials are the high frequency operability and high magnetic anisotropy. High uniaxial anisotropy is one of the most important properties for these materials. There are many methods to achieve high anisotropy energy (Hk) which include sputtering with presence of magnetic field, exchange bias and oblique angle sputtering.

This research project focuses on analyzing different growth techniques of thin films of Cobalt, Zirconium Tantalum Boron (CZTB) and the quality of the films resulted. The measurements include magnetic moment measurements using a Vibrating Sample Magnetometer, electrical measurements using 4 point resistivity methods and structural characterization using Scanning Electron Microscopy. Subtle changes in the growth mechanism result in different properties of these films and they are most suited for certain applications.

The growth methods presented in this research are oblique angled sputtering with localized magnetic field and oblique sputtering without presence of magnetic field. The uniaxial anisotropy can be controlled by changing the angle during sputtering. The resulting film of CZTB is tested for magnetic anisotropy and soft magnetism at room temperature by using Lakeshore 7500 Vibrating Sample Magnetometer. The results are presented, analyzed and explained using characterization techniques. Future work includes magnetic field presence during deposition, magnetic devices of this film with giga hertz range operating frequencies.
ContributorsTummalapalli, Sridutt (Author) / Yu, Hongbin (Thesis advisor) / Jiang, Hanqing (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2015
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Description
Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have

Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical.

The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation.

Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR.

Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths.

Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.
ContributorsKulkarni, Niranjan (Author) / Vrudhula, Sarma (Thesis advisor) / Colbourn, Charles (Committee member) / Seo, Jae-Sun (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Created2015
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Description
While SPICE circuit simulation software gives researchers and industry accurate information regarding the behavior and characteristics of circuits, the auditory effect of SPICE circuit simulation on audio circuits is not well documented. This project takes a thoroughly analyzed and popular audio effect circuit called the Ibanez Tubescreamer and simulates its

While SPICE circuit simulation software gives researchers and industry accurate information regarding the behavior and characteristics of circuits, the auditory effect of SPICE circuit simulation on audio circuits is not well documented. This project takes a thoroughly analyzed and popular audio effect circuit called the Ibanez Tubescreamer and simulates its distortion effect on a .wav file in order to hear the effect of SPICE simulation. Specifically, the TS-808 schematic is drawn in the SPICE program LTSPICE and simulated using generated sinusoids and recorded .wav files. Specific components are imported using .MODEL and .SUBCKT to accurately represent the diodes, bipolar transistors, op amps, and other components in order to hear how each component affects the response. Various transient responses are extracted as .wav files and assembled as figures in order to characterize the result of the circuit on the input. Once the actual circuit is built and debugged, all of the same transient analysis is applied and then compared to the SPICE simulation figures gathered in the digital simulation. These results are then compared along with a subjective hearing test of the digital simulation and analog circuit in order to test the validity of the SPICE simulations. The digital simulations reveal that the distortion follows the signature characteristics of Ibanez Tubescreamer which shows that SPICE simulation will give insight into the real effects of audio circuits modeled in SPICE programs. Diodes--such as Silicon, Germanium, Zener, Red LEDs and Blue LEDs--can dramatically change the waveforms and sound of the inputs within the circuit where as the Op-amps--such as the JRC4558, TL072, and NE5532--have little to no effect on the waveforms and subjective effects on the output .wav files. After building the circuit and hearing the difference between the analog circuit and digital simulation, the differences between the two are apparent but very similar in nature--proving that the SPICE simulation can give meaningful insight into the sound of the actual analog circuit. Some of the differences can be explained by the variance of equipment and environment used in recording and playback. Since this project did not use high fidelity audio recording equipment and consistency in the equipment used for playback, it is uncertain if the simulation and actual circuit could be classified as completely accurate. Any further work on the project would be recording and playing back in a constant environment and looking into a wider range of specific components instead of looking into one permutation.
ContributorsMacias, Cole Thomas (Author) / Goryll, Michael (Thesis director) / Yu, Shimeng (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2015-12