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Digital Modeling of Analog Effect Circuits

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While SPICE circuit simulation software gives researchers and industry accurate information regarding the behavior and characteristics of circuits, the auditory effect of SPICE circuit simulation on audio circuits is not well documented. This project takes a thoroughly analyzed and popular

While SPICE circuit simulation software gives researchers and industry accurate information regarding the behavior and characteristics of circuits, the auditory effect of SPICE circuit simulation on audio circuits is not well documented. This project takes a thoroughly analyzed and popular audio effect circuit called the Ibanez Tubescreamer and simulates its distortion effect on a .wav file in order to hear the effect of SPICE simulation. Specifically, the TS-808 schematic is drawn in the SPICE program LTSPICE and simulated using generated sinusoids and recorded .wav files. Specific components are imported using .MODEL and .SUBCKT to accurately represent the diodes, bipolar transistors, op amps, and other components in order to hear how each component affects the response. Various transient responses are extracted as .wav files and assembled as figures in order to characterize the result of the circuit on the input. Once the actual circuit is built and debugged, all of the same transient analysis is applied and then compared to the SPICE simulation figures gathered in the digital simulation. These results are then compared along with a subjective hearing test of the digital simulation and analog circuit in order to test the validity of the SPICE simulations. The digital simulations reveal that the distortion follows the signature characteristics of Ibanez Tubescreamer which shows that SPICE simulation will give insight into the real effects of audio circuits modeled in SPICE programs. Diodes--such as Silicon, Germanium, Zener, Red LEDs and Blue LEDs--can dramatically change the waveforms and sound of the inputs within the circuit where as the Op-amps--such as the JRC4558, TL072, and NE5532--have little to no effect on the waveforms and subjective effects on the output .wav files. After building the circuit and hearing the difference between the analog circuit and digital simulation, the differences between the two are apparent but very similar in nature--proving that the SPICE simulation can give meaningful insight into the sound of the actual analog circuit. Some of the differences can be explained by the variance of equipment and environment used in recording and playback. Since this project did not use high fidelity audio recording equipment and consistency in the equipment used for playback, it is uncertain if the simulation and actual circuit could be classified as completely accurate. Any further work on the project would be recording and playing back in a constant environment and looking into a wider range of specific components instead of looking into one permutation.

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2015-12

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Modeling and simulation tools for aging effects in scaled CMOS design

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The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress

The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI that enable aging simulation under all possible stress conditions. Key features of this work are compact models to predict BTI aging based on Reaction-Diffusion theory when the stress voltage is varying. The results to both reaction-diffusion (RD) and trapping-detrapping (TD) mechanisms are presented to cover underlying physics. Silicon validation of these models is performed at 28nm, 45nm and 65nm technology nodes, at both device and circuit levels. Efficient simulation leveraging the BTI models under DVS and random input waveform is applied to both digital and analog representative circuits such as ring oscillators and LNA. Both physical mechanisms are combined into a unified model which improves prediction accuracy at 45nm and 65nm nodes. Critical failure condition is also illustrated based on NBTI and PBTI at 28nm. A comprehensive picture for duty cycle shift is shown. DC stress under clock gating schemes results in monotonic shift in duty cycle which an AC stress causes duty cycle to converge close to 50% value. Proposed work provides a general and comprehensive solution to aging analysis under random stress patterns under BTI.

Channel hot carrier (CHC) is another dominant degradation mechanism which affects analog and mixed signal circuits (AMS) as transistor operates continuously in saturation condition. New model is proposed to account for e-e scattering in advanced technology nodes due to high gate electric field. The model is validated with 28nm and 65nm thick oxide data for different stress voltages. It demonstrates shift in worst case CHC condition to Vgs=Vds from Vgs=0.5Vds. A novel iteration based aging simulation framework for AMS designs is proposed which eliminates limitation for conventional reliability tools. This approach helps us identify a unique positive feedback mechanism termed as Bias Runaway. Bias runaway, is rapid increase of the bias voltage in AMS circuits which occurs when the feedback between the bias current and the effect of channel hot carrier turns into positive. The degradation of CHC is a gradual process but under specific circumstances, the degradation rate can be dramatically accelerated. Such a catastrophic phenomenon is highly sensitive to the initial operation condition, as well as transistor gate length. Based on 65nm silicon data, our work investigates the critical condition that triggers bias runaway, and the impact of gate length tuning. We develop new compact models as well as the simulation methodology for circuit diagnosis, and propose design solutions and the trade-offs to avoid bias runaway, which is vitally important to reliable AMS designs.

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2014