Matching Items (4)
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- All Subjects: Digital-to-analog converters
- All Subjects: Digital-to-analog converters--Design and construction.
- All Subjects: Sensor Networks
- Genre: Masters Thesis
- Creators: Kitchen, Jennifer
- Member of: ASU Electronic Theses and Dissertations
Description
Digital to analog converters (DACs) find widespread use in communications equipment. Most commercially available DAC's which are intended to be used in transmitter applications come in a dual configuration for carrying the in phase (I) and quadrature (Q) data and feature on chip digital mixing. Digital mixing offers many benefits concerning I and Q matching but has one major drawback; the update rate of the DAC must be higher than the intermediate frequency (IF) which is most commonly a factor of 4. This drawback motivates the need for interpolation so that a low update rate can be used for components preceding the DACs. In this thesis the design of an interpolating DAC integrated circuit (IC) to be used in a transmitter application for generating a 100MHz IF is presented. Many of the transistor level implementations are provided. The tradeoffs in the design are analyzed and various options are discussed. This thesis provides a basic foundation for designing an IC of this nature and will give the reader insight into potential areas of further research. At the time of this writing the chip is in fabrication therefore this document does not contain test results.
ContributorsNixon, Cliff (Author) / Bakkaloglu, Bertan (Thesis advisor) / Arizona State University (Publisher)
Created2013
Description
Wireless video sensor networks has been examined and evaluated for wide range
of applications comprising of video surveillance, video tracking, computer vision, remote
live video and control. The reason behind importance of sensor nodes is its ease
of implementation, ability to operate in adverse environments, easy to troubleshoot,
repair and the high performance level. The biggest challenges with the architectural
design of wireless video sensor networks are power consumption, node failure,
throughput, durability and scalability. The whole project here is to create a gateway
node to integrate between "Internet of things" framework and wireless sensor network.
Our Flexi-Wireless Video Sensor Node Platform (WVSNP) is a low cost, low
power and compatible with traditional sensor network where the main focus was on
maximizing throughput or minimizing node deployment. My task here in this project
was to address the challenges of video power consumption for wireless video sensor
nodes. While addressing the challenges, I performed analysis of predicting the nodes
durability when it is battery operated and to choose appropriate design parameters.
I created a small optimized image to boot up Wandboard DUAL/QUAD board, capture
videos in small/big chunks from the board. The power analysis was performed
for only capturing scenarios, playback of reference videos and, live capturing and realtime
playing of videos on WVSNP player. Each sensor node in sensor network are
battery operated and runs without human intervention. Thus to predict nodes durability,
for dierent video size and format, I have collected power consumption results
and based on this I have provided some recommendation of HW/SW architecture.
i
of applications comprising of video surveillance, video tracking, computer vision, remote
live video and control. The reason behind importance of sensor nodes is its ease
of implementation, ability to operate in adverse environments, easy to troubleshoot,
repair and the high performance level. The biggest challenges with the architectural
design of wireless video sensor networks are power consumption, node failure,
throughput, durability and scalability. The whole project here is to create a gateway
node to integrate between "Internet of things" framework and wireless sensor network.
Our Flexi-Wireless Video Sensor Node Platform (WVSNP) is a low cost, low
power and compatible with traditional sensor network where the main focus was on
maximizing throughput or minimizing node deployment. My task here in this project
was to address the challenges of video power consumption for wireless video sensor
nodes. While addressing the challenges, I performed analysis of predicting the nodes
durability when it is battery operated and to choose appropriate design parameters.
I created a small optimized image to boot up Wandboard DUAL/QUAD board, capture
videos in small/big chunks from the board. The power analysis was performed
for only capturing scenarios, playback of reference videos and, live capturing and realtime
playing of videos on WVSNP player. Each sensor node in sensor network are
battery operated and runs without human intervention. Thus to predict nodes durability,
for dierent video size and format, I have collected power consumption results
and based on this I have provided some recommendation of HW/SW architecture.
i
ContributorsShah, Tejas (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Since the inception of Internet of Things (IoT) framework, the amount of interaction between electronic devices has tremendously increased and the ease of implementing software between such devices has bettered. Such data exchange between devices, whether between Node to Server or Node to Node, has paved way for creating new business models. Wireless Video Sensor Network Platforms are being used to monitor and understand the surroundings better. Both hardware and software supporting such devices have become much smaller and yet stronger to enable these. Specifically, the invention of better software that enable Wireless data transfer have become more simpler and lightweight technologies such as HTML5 for video rendering, Common Gateway Interface(CGI) scripts enabling interactions between client and server and WebRTC from Google for peer to peer interactions. The role of web browsers in enabling these has been vastly increasing.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
Although HTTP is the most reliable and consistent data transfer protocol for such interactions, the most important underlying challenge with such platforms is the performance based on power consumption and latency in data transfer.
In the scope of this thesis, two applications using CGI and WebRTC for data transfer over HTTP will be presented and the power consumption by the peripherals in transmitting the data and the possible implications for those will be discussed.
ContributorsRentala, Sri Harsha (Author) / Reisslein, Martin (Thesis advisor) / Kitchen, Jennifer (Committee member) / McGarry, Michael (Committee member) / Arizona State University (Publisher)
Created2016