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Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The end of the nineteenth century was an exhilarating and revolutionary era for the flute. This period is the Second Golden Age of the flute, when players and teachers associated with the Paris Conservatory developed what would be considered the birth of the modern flute school. In addition, the founding

The end of the nineteenth century was an exhilarating and revolutionary era for the flute. This period is the Second Golden Age of the flute, when players and teachers associated with the Paris Conservatory developed what would be considered the birth of the modern flute school. In addition, the founding in 1871 of the Société Nationale de Musique by Camille Saint-Saëns (1835-1921) and Romain Bussine (1830-1899) made possible the promotion of contemporary French composers. The founding of the Société des Instruments à Vent by Paul Taffanel (1844-1908) in 1879 also invigorated a new era of chamber music for wind instruments. Within this groundbreaking environment, Mélanie Hélène Bonis (pen name Mel Bonis) entered the Paris Conservatory in 1876, under the tutelage of César Franck (1822-1890). Many flutists are dismayed by the scarcity of repertoire for the instrument in the Romantic and post-Romantic traditions; they make up for this absence by borrowing the violin sonatas of Gabriel Fauré (1845-1924) and Franck. The flute and piano works of Mel Bonis help to fill this void with music composed originally for flute. Bonis was a prolific composer with over 300 works to her credit, but her works for flute and piano have not been researched or professionally recorded in the United States before the present study. Although virtually unknown today in the American flute community, Bonis's music received much acclaim from her contemporaries and deserves a prominent place in the flutist's repertoire. After a brief biographical introduction, this document examines Mel Bonis's musical style and describes in detail her six works for flute and piano while also offering performance suggestions.
ContributorsDaum, Jenna Elyse (Author) / Buck, Elizabeth (Thesis advisor) / Holbrook, Amy (Committee member) / Micklich, Albie (Committee member) / Schuring, Martin (Committee member) / Norton, Kay (Committee member) / Arizona State University (Publisher)
Created2013
ContributorsDaval, Charles (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-26
Description
Despite the wealth of folk music traditions in Portugal and the importance of the clarinet in the music of bandas filarmonicas, it is uncommon to find works featuring the clarinet using Portuguese folk music elements. In the interest of expanding this type of repertoire, three new works were commissioned from

Despite the wealth of folk music traditions in Portugal and the importance of the clarinet in the music of bandas filarmonicas, it is uncommon to find works featuring the clarinet using Portuguese folk music elements. In the interest of expanding this type of repertoire, three new works were commissioned from three different composers. The resulting works are Seres Imaginarios 3 by Luis Cardoso; Delirio Barroco by Tiago Derrica; and Memória by Pedro Faria Gomes. In an effort to submit these new works for inclusion into mainstream performance literature, the author has recorded these works on compact disc. This document includes interview transcripts with each composer, providing first-person discussion of each composition, as well as detailed biographical information on each composer. To provide context, the author has included a brief discussion on Portuguese folk music, and in particular, the role that the clarinet plays in Portuguese folk music culture.
ContributorsFerreira, Wesley (Contributor) / Spring, Robert S (Thesis advisor) / Bailey, Wayne (Committee member) / Gardner, Joshua (Committee member) / Hill, Gary (Committee member) / Schuring, Martin (Committee member) / Solis, Theodore (Committee member) / Arizona State University (Publisher)
Created2013
ContributorsMatthews, Eyona (Performer) / Yoo, Katie Jihye (Performer) / Roubison, Ryan (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-25
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DescriptionThe purpose of this project is to explore the influence of folk music in guitar compositions by Manuel Ponce from 1923 to 1932. It focuses on his Tres canciones populares mexicanas and Tropico and Rumba.
ContributorsGarcia Santos, Arnoldo (Author) / Koonce, Frank (Thesis advisor) / Rogers, Rodney (Committee member) / Rotaru, Catalin (Committee member) / Arizona State University (Publisher)
Created2014
ContributorsHoeckley, Stephanie (Performer) / Lee, Juhyun (Performer) / ASU Library. Music Library (Publisher)
Created2018-03-24
ContributorsBurton, Charlotte (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-08
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Description
Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One

Network-on-Chip (NoC) architectures have emerged as the solution to the on-chip communication challenges of multi-core embedded processor architectures. Design space exploration and performance evaluation of a NoC design requires fast simulation infrastructure. Simulation of register transfer level model of NoC is too slow for any meaningful design space exploration. One of the solutions to reduce the speed of simulation is to increase the level of abstraction. SystemC TLM2.0 provides the capability to model hardware design at higher levels of abstraction with trade-off of simulation speed and accuracy. In this thesis, SystemC TLM2.0 models of NoC routers are developed at three levels of abstraction namely loosely-timed, approximately-timed, and cycle accurate. Simulation speed and accuracy of these three models are evaluated by a case study of a 4x4 mesh NoC.
ContributorsArlagadda Narasimharaju, Jyothi Swaroop (Author) / Chatha, Karamvir S (Thesis advisor) / Sen, Arunabha (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2012
ContributorsDruesedow, Elizabeth (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-07