Matching Items (4)
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- All Subjects: Ionizing Radiation
- Creators: Holbert, Keith E.
- Member of: ASU Electronic Theses and Dissertations
- Resource Type: Text
Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011
Description
Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices.
This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.
The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.
This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario.
The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory.
ContributorsTaggart, Jennifer Lynn (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Flash memories are critical for embedded devices to operate properly but are susceptible to radiation effects, which make flash memory a key factor to improve the reliability of circuitry. This thesis describes the simulation techniques used to analyze and predict total ionizing dose (TID) effects on 90-nm technology Silicon Storage Technology (SST) SuperFlash Generation 3 devices. Silvaco Atlas is used for both device level design and simulation purposes.
The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms.
The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad.
The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad.
The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms.
The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad.
The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad.
ContributorsChen, Yitao (Author) / Holbert, Keith E. (Thesis advisor) / Clark, Lawrence T. (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2016